Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0291
A. Gu, A. Andreyev, M. Terada, Bernice Zee, Syahirah Mohammad-Zulkifli, Yanjing Yang
Over the past decade, 3D X-ray technique has played a critical role in semiconductor package failure analysis (FA), primarily owing to its non-destructive nature and high resolution capability [1,2]. As novel complex IC packages soar in recent years [3,4], X-ray failure analysis faces increasing challenges in imaging new advanced packages because IC interconnects are more densely packed in larger platforms. It takes several hours to overnight to image fault regions at high resolution or the crucial details of a defect remain undetected. A high-productivity X-ray solution is required to substantially speed up data acquisition while maintaining image quality. In this paper, we propose a new deep learning high-resolution reconstruction (DLHRR) method, capable of speeding up data acquisition by at least a factor of four through the implementation of pretrained neural networks. We will demonstrate that DLHRR extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) method, which is sensitive to noise and prone to the aliasing image artifacts. Several semiconductor packages and a commercial smartwatch battery module will be analyzed using the proposed technique. Up to 10x scan throughput improvement was demonstrated on a commercial IC package. Without the need of any additional X-ray beam-line hardware, the proposed method can provide a viable and affordable solution to turbocharge X-ray failure analysis.
{"title":"Accelerate Your 3D X-ray Failure Analysis by Deep Learning High Resolution Reconstruction","authors":"A. Gu, A. Andreyev, M. Terada, Bernice Zee, Syahirah Mohammad-Zulkifli, Yanjing Yang","doi":"10.31399/asm.cp.istfa2021p0291","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0291","url":null,"abstract":"\u0000 Over the past decade, 3D X-ray technique has played a critical role in semiconductor package failure analysis (FA), primarily owing to its non-destructive nature and high resolution capability [1,2]. As novel complex IC packages soar in recent years [3,4], X-ray failure analysis faces increasing challenges in imaging new advanced packages because IC interconnects are more densely packed in larger platforms. It takes several hours to overnight to image fault regions at high resolution or the crucial details of a defect remain undetected. A high-productivity X-ray solution is required to substantially speed up data acquisition while maintaining image quality. In this paper, we propose a new deep learning high-resolution reconstruction (DLHRR) method, capable of speeding up data acquisition by at least a factor of four through the implementation of pretrained neural networks. We will demonstrate that DLHRR extracts signals from low-dose data more efficiently than the conventional Feldkamp-Davis-Kress (FDK) method, which is sensitive to noise and prone to the aliasing image artifacts. Several semiconductor packages and a commercial smartwatch battery module will be analyzed using the proposed technique. Up to 10x scan throughput improvement was demonstrated on a commercial IC package. Without the need of any additional X-ray beam-line hardware, the proposed method can provide a viable and affordable solution to turbocharge X-ray failure analysis.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116531974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0059
Daniel Johnson, Po-Wei Hsu, Chengjie Xi, N. Asadizanjani
The supply chain of the semiconductor industry is experiencing painful growth and advancement in chip development with the help of recently passed U.S legislation and funding to address a chip shortage. However, it is not without some drawbacks, one of which is the challenge of maintaining control over the manufacturing quality throughout the entire process. As a result of this, physical inspection for hardware security is a necessity to assure the semiconductor devices. In this paper, various physical inspection methods are reviewed and scanning acoustic microscopy (SAM) is proved to be the ideal physical inspection method to minimize the possibility of counterfeits which might be the feasible solution in detecting counterfeits on a large scale.
{"title":"Scanning Acoustic Microscopy Package Fingerprint Extraction for Integrate Circuit Hardware Assurance","authors":"Daniel Johnson, Po-Wei Hsu, Chengjie Xi, N. Asadizanjani","doi":"10.31399/asm.cp.istfa2021p0059","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0059","url":null,"abstract":"\u0000 The supply chain of the semiconductor industry is experiencing painful growth and advancement in chip development with the help of recently passed U.S legislation and funding to address a chip shortage. However, it is not without some drawbacks, one of which is the challenge of maintaining control over the manufacturing quality throughout the entire process. As a result of this, physical inspection for hardware security is a necessity to assure the semiconductor devices. In this paper, various physical inspection methods are reviewed and scanning acoustic microscopy (SAM) is proved to be the ideal physical inspection method to minimize the possibility of counterfeits which might be the feasible solution in detecting counterfeits on a large scale.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"507 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122755166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0206
J. Li, K. Brew, K. Cheng, V. Chan, N. Arnold, A. Gasasira, R. Pujari, J. Demarest, M. Iwatake, L. Tierney, O. Ogundipe, K. Toole, N. Li
The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the mushroom type PCM cells based on Ge2Sb2Te5 at nanoscale by low angle annular dark field (LAADF) STEM imaging technique as well as energy dispersive X-ray spectroscopy (EDX) to study the changes in microstructure and elemental distributions in PCM mushroom cells before and after SET and RESET conditions. We describe the microscope settings used for LAADF image formation to reveal the amorphous dome in RESET device and discuss the application example in failure analysis of PCM test device.
{"title":"Low Angle Annular Dark Field Scanning Transmission Electron Microscopy Analysis of Phase Change Material","authors":"J. Li, K. Brew, K. Cheng, V. Chan, N. Arnold, A. Gasasira, R. Pujari, J. Demarest, M. Iwatake, L. Tierney, O. Ogundipe, K. Toole, N. Li","doi":"10.31399/asm.cp.istfa2021p0206","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0206","url":null,"abstract":"\u0000 The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the mushroom type PCM cells based on Ge2Sb2Te5 at nanoscale by low angle annular dark field (LAADF) STEM imaging technique as well as energy dispersive X-ray spectroscopy (EDX) to study the changes in microstructure and elemental distributions in PCM mushroom cells before and after SET and RESET conditions. We describe the microscope settings used for LAADF image formation to reveal the amorphous dome in RESET device and discuss the application example in failure analysis of PCM test device.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"51 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114042090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0150
E. Kim, Jaeyun Lee, Jihyun Lee
This paper demonstrates how to localize metal-to-metal short failures in DRAM, where defects can occur over a large area including the aluminum layer, by using the means of mechanical grinding, plasma FIB delayering, and EBIRCH (Electron Beam Induced Resistance Change). Our experiments show that a uniform mechanical grinding of an aluminum layer, and DX PFIB delayering, results in a high quality planer surface in the target layer and site, as the slope created during the grinding is compensated by PFIB delayering. This approach has advantages that are conducive to EBIRCH analysis. First, the target layer can be prepared at any given location (site-free). Second, the defective layer can be delayered to a desired depth without damage (layer-free). Last, after delayering, the surface of the device becomes evenly flat enough to allow the electron beam to evenly penetrate the device for EBIRCH analysis (higher-flatness).With the use of more advanced device preparation methods, EBIRCH analysis has a higher chance of successfully localizing metal line/via shorts even in a large region, which includes the aluminum layer.
{"title":"Plasma FIB Delayering and Nanoprobing with EBIRCH for Localizing Metal Shorts in DRAM","authors":"E. Kim, Jaeyun Lee, Jihyun Lee","doi":"10.31399/asm.cp.istfa2021p0150","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0150","url":null,"abstract":"\u0000 This paper demonstrates how to localize metal-to-metal short failures in DRAM, where defects can occur over a large area including the aluminum layer, by using the means of mechanical grinding, plasma FIB delayering, and EBIRCH (Electron Beam Induced Resistance Change). Our experiments show that a uniform mechanical grinding of an aluminum layer, and DX PFIB delayering, results in a high quality planer surface in the target layer and site, as the slope created during the grinding is compensated by PFIB delayering. This approach has advantages that are conducive to EBIRCH analysis. First, the target layer can be prepared at any given location (site-free). Second, the defective layer can be delayered to a desired depth without damage (layer-free). Last, after delayering, the surface of the device becomes evenly flat enough to allow the electron beam to evenly penetrate the device for EBIRCH analysis (higher-flatness).With the use of more advanced device preparation methods, EBIRCH analysis has a higher chance of successfully localizing metal line/via shorts even in a large region, which includes the aluminum layer.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128222423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0023
Anna Safont-Andreu, C. Burmer, Konstantin Schekotihin
Fault analysis is a complex task that requires electrical engineers to perform various analyses to detect and localize a physical defect. The analysis process is very knowledge-intensive and must be precisely documented to report the issue to customers as well as to ensure the best possible reuse of the acquired experience in similar future analyses. However, writing unambiguous documentation can be complicated for many reasons, such as selecting details and results to be presented in a report, or the naming of terms and their definition. To avoid some of these issues, FA engineers must agree on a clearly defined terminology specifying methods, physical faults and their electrical signatures, tools, and relations between them. Moreover, to allow FA software systems to use this terminology, it must be stored in a format that can be interpreted similarly by both engineers and software. This paper presents an approach that solves these challenges by using an ontology describing FA-relevant terminology using a logic-based representation. The latter guarantees the same interpretation of the defined terms by engineers and software systems, which can use it to perform various tasks like text classification, information retrieval, or workflow verification.
{"title":"Using Ontologies in Failure Analysis","authors":"Anna Safont-Andreu, C. Burmer, Konstantin Schekotihin","doi":"10.31399/asm.cp.istfa2021p0023","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0023","url":null,"abstract":"\u0000 Fault analysis is a complex task that requires electrical engineers to perform various analyses to detect and localize a physical defect. The analysis process is very knowledge-intensive and must be precisely documented to report the issue to customers as well as to ensure the best possible reuse of the acquired experience in similar future analyses. However, writing unambiguous documentation can be complicated for many reasons, such as selecting details and results to be presented in a report, or the naming of terms and their definition. To avoid some of these issues, FA engineers must agree on a clearly defined terminology specifying methods, physical faults and their electrical signatures, tools, and relations between them. Moreover, to allow FA software systems to use this terminology, it must be stored in a format that can be interpreted similarly by both engineers and software.\u0000 This paper presents an approach that solves these challenges by using an ontology describing FA-relevant terminology using a logic-based representation. The latter guarantees the same interpretation of the defined terms by engineers and software systems, which can use it to perform various tasks like text classification, information retrieval, or workflow verification.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114791494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0096
S. M. Oliver, D. Martynowych, M. Turner, David A. Hopper, R. Walsworth, E. Levine
The increasing trend for industry adoption of three-dimensional (3D) microelectronics packaging necessitates the development of new and innovative approaches to failure analysis. To that end, our team is developing a tool called the quantum diamond microscope (QDM) that leverages an ensemble of nitrogenvacancy (NV) centers in diamond for simultaneous wide fieldof- view, high spatial resolution, vector magnetic field imaging of microelectronics under ambient conditions [1,2]. Here, we present QDM measurements of two-dimensional (2D) current distributions in an 8 nm process node flip chip integrated circuit (IC) and 3D current distributions in a custom, multi-layer printed circuit board (PCB). Magnetic field emanations from the C4 bumps in the flip chip dominate the QDM measurements, but these prove to be useful for image registration and can be subtracted to resolve adjacent current traces on the micron scale in the die. Vias, an important component in 3D ICs, display only Bx and By magnetic fields due to their vertical orientation, which are challenging to detect with magnetometers that traditionally only measure the Bz component of the magnetic field (orthogonal to the IC surface). Using the multi-layer PCB, we demonstrate that the QDM's ability to simultaneously measure Bx, By, and Bz magnetic field components in 3D structures is advantageous for resolving magnetic fields from vias as current passes between layers. The height difference between two conducting layers is determined by the magnetic field images and agrees with the PCB design specifications. In our initial steps to provide further z depth information for current sources in complex 3D circuits using the QDM, we demonstrate that, due to the linear properties of Maxwell's equations, magnetic field images of individual layers can be subtracted from the magnetic field image of the total structure. This allows for isolation of signal from individual layers in the device that can be used to map embedded current paths via solution of the 2D magnetic inverse. Such an approach suggests an iterative analysis protocol that utilizes neural networks trained with images containing various classes of current sources, standoff distances, and noise integrated with prior information of ICs to subtract current sources layer by layer and provide z depth information. This initial study demonstrates the usefulness of the QDM for failure analysis and points to technical advances of this technique to come.
{"title":"Vector Magnetic Current Imaging of an 8 nm Process Node Chip and 3D Current Distributions Using the Quantum Diamond Microscope","authors":"S. M. Oliver, D. Martynowych, M. Turner, David A. Hopper, R. Walsworth, E. Levine","doi":"10.31399/asm.cp.istfa2021p0096","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0096","url":null,"abstract":"\u0000 The increasing trend for industry adoption of three-dimensional (3D) microelectronics packaging necessitates the development of new and innovative approaches to failure analysis. To that end, our team is developing a tool called the quantum diamond microscope (QDM) that leverages an ensemble of nitrogenvacancy (NV) centers in diamond for simultaneous wide fieldof- view, high spatial resolution, vector magnetic field imaging of microelectronics under ambient conditions [1,2]. Here, we present QDM measurements of two-dimensional (2D) current distributions in an 8 nm process node flip chip integrated circuit (IC) and 3D current distributions in a custom, multi-layer printed circuit board (PCB). Magnetic field emanations from the C4 bumps in the flip chip dominate the QDM measurements, but these prove to be useful for image registration and can be subtracted to resolve adjacent current traces on the micron scale in the die. Vias, an important component in 3D ICs, display only Bx and By magnetic fields due to their vertical orientation, which are challenging to detect with magnetometers that traditionally only measure the Bz component of the magnetic field (orthogonal to the IC surface). Using the multi-layer PCB, we demonstrate that the QDM's ability to simultaneously measure Bx, By, and Bz magnetic field components in 3D structures is advantageous for resolving magnetic fields from vias as current passes between layers. The height difference between two conducting layers is determined by the magnetic field images and agrees with the PCB design specifications. In our initial steps to provide further z depth information for current sources in complex 3D circuits using the QDM, we demonstrate that, due to the linear properties of Maxwell's equations, magnetic field images of individual layers can be subtracted from the magnetic field image of the total structure. This allows for isolation of signal from individual layers in the device that can be used to map embedded current paths via solution of the 2D magnetic inverse. Such an approach suggests an iterative analysis protocol that utilizes neural networks trained with images containing various classes of current sources, standoff distances, and noise integrated with prior information of ICs to subtract current sources layer by layer and provide z depth information. This initial study demonstrates the usefulness of the QDM for failure analysis and points to technical advances of this technique to come.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0324
Kuang Shien Lee, Lai Khei Kuan
MIM (Metal-Insulator-Metal) capacitor is a capacitor fabricated between metal layers and usually in an array form. Since it is usually buried within stack of back-end metal layers, neither front side nor backside FA fault isolation techniques can easily pinpoint the defect location of a failing MIM capacitor. A preliminary fault isolation (FI) often needs to be performed by biasing the desired failing state setup to highlight the difference(s) of FI site(s) between failing unit & reference. Then, a detailed study of the CAD (Computer Aided Design) schematic and die layout focusing on the difference(s) of FI site(s) will lead to a more in-depth analyses such as Focused Ion-Beam (FIB) circuit edit, micro-probing/nano-probing, Voltage Contrast (VC) and other available FA techniques to further identify the defective MIM capacitor. Once the defective MIM capacitor was identified, FIB cross-section or delayering can be performed to inspect the physical defect on the MIM capacitor. This paper presents the FA approach and challenges in successfully finding MIM capacitor failures.
{"title":"FA Approach on MIM (Metal-Insulator-Metal) Capacitor Failures","authors":"Kuang Shien Lee, Lai Khei Kuan","doi":"10.31399/asm.cp.istfa2021p0324","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0324","url":null,"abstract":"\u0000 MIM (Metal-Insulator-Metal) capacitor is a capacitor fabricated between metal layers and usually in an array form. Since it is usually buried within stack of back-end metal layers, neither front side nor backside FA fault isolation techniques can easily pinpoint the defect location of a failing MIM capacitor. A preliminary fault isolation (FI) often needs to be performed by biasing the desired failing state setup to highlight the difference(s) of FI site(s) between failing unit & reference. Then, a detailed study of the CAD (Computer Aided Design) schematic and die layout focusing on the difference(s) of FI site(s) will lead to a more in-depth analyses such as Focused Ion-Beam (FIB) circuit edit, micro-probing/nano-probing, Voltage Contrast (VC) and other available FA techniques to further identify the defective MIM capacitor. Once the defective MIM capacitor was identified, FIB cross-section or delayering can be performed to inspect the physical defect on the MIM capacitor. This paper presents the FA approach and challenges in successfully finding MIM capacitor failures.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128028980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0388
K. Chung, Shaun Nicholson, Soumya Mittal, M. Parley, Gaurav Veda, Manish Sharma, Matt Knowles, Wu-Tung Cheng
In this paper, we present a diagnosis resolution improvement methodology for scan-based tests. We achieve 89% reduction in the number of suspect diagnosis locations and a 2.4X increase in the number of highly resolved diagnosis results. We suffer a loss in accuracy of 1.5%. These results were obtained from an extensive silicon study. We use data from pilot wafers and 11 other wafers at the leading-edge technology node and check against failure analysis results from 203 cases. This resolution improvement is achieved by considering the diagnosis problem at the level of a population (e.g. a wafer) of failing die instead of analyzing each failing die completely independently as has been done traditionally. Higher diagnosis resolution is critical for speeding up the yield learning from manufacturing test and failure analysis flows.
{"title":"Improving Diagnosis Resolution with Population Level Statistical Diagnosis","authors":"K. Chung, Shaun Nicholson, Soumya Mittal, M. Parley, Gaurav Veda, Manish Sharma, Matt Knowles, Wu-Tung Cheng","doi":"10.31399/asm.cp.istfa2021p0388","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0388","url":null,"abstract":"\u0000 In this paper, we present a diagnosis resolution improvement methodology for scan-based tests. We achieve 89% reduction in the number of suspect diagnosis locations and a 2.4X increase in the number of highly resolved diagnosis results. We suffer a loss in accuracy of 1.5%. These results were obtained from an extensive silicon study. We use data from pilot wafers and 11 other wafers at the leading-edge technology node and check against failure analysis results from 203 cases. This resolution improvement is achieved by considering the diagnosis problem at the level of a population (e.g. a wafer) of failing die instead of analyzing each failing die completely independently as has been done traditionally. Higher diagnosis resolution is critical for speeding up the yield learning from manufacturing test and failure analysis flows.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134200298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0454
Koutaro Kikukawa, Natsuki Sugaya, Shigeru Ohno, Y. Tomita
In this paper, we report the results of a quantitative evaluation of the resolution and detectability on images obtained by SAT through silicon wafers with the thicknesses of 775 and 100 µm by transducers with the most appropriate focal length.
{"title":"Quantitative Evaluation of Bonded Silicon Wafer by Scanning Acoustic Tomography","authors":"Koutaro Kikukawa, Natsuki Sugaya, Shigeru Ohno, Y. Tomita","doi":"10.31399/asm.cp.istfa2021p0454","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0454","url":null,"abstract":"\u0000 In this paper, we report the results of a quantitative evaluation of the resolution and detectability on images obtained by SAT through silicon wafers with the thicknesses of 775 and 100 µm by transducers with the most appropriate focal length.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131117284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-31DOI: 10.31399/asm.cp.istfa2021p0377
Andrew C. Sabate, Rommel Estores
Unique single failing device is common for customer returns and reliability failures. When the initial and iterative Automatic Test Pattern Generator (ATPG) could not provide a sufficient diagnostic resolution, it can become quite challenging for the analyst to determine the failure mechanism in an efficient and effective way. Fault isolation could be performed in combination with the diagnosis results but there are cases with mismatch between the results (location, fault type, suspect nets). When the diagnostic resolution is low, the probability for such mismatches are high. This paper proposes an approach to increase the diagnostic resolution by utilizing a high-resolution targeted pattern (HRT) and single shot logic (SSL) patterns. Two cases will be discussed in the paper to highlight this approach and show in detail how it was utilized on actual failing units.
独特的单故障设备是常见的客户退货和可靠性故障。当初始的和迭代的自动测试模式生成器(Automatic Test Pattern Generator, ATPG)不能提供足够的诊断解决方案时，分析人员以高效和有效的方式确定故障机制就变得相当具有挑战性。故障隔离可以结合诊断结果进行，但也存在结果(位置、故障类型、可疑网络)不匹配的情况。当诊断分辨率较低时，这种不匹配的概率很高。本文提出了一种利用高分辨率目标模式(HRT)和单镜头逻辑模式(SSL)来提高诊断分辨率的方法。本文将讨论两个案例，以突出这种方法，并详细展示如何在实际的故障单元上使用它。
{"title":"Maximizing ATPG Diagnosis Resolution on Unique Single Failing Devices","authors":"Andrew C. Sabate, Rommel Estores","doi":"10.31399/asm.cp.istfa2021p0377","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2021p0377","url":null,"abstract":"\u0000 Unique single failing device is common for customer returns and reliability failures. When the initial and iterative Automatic Test Pattern Generator (ATPG) could not provide a sufficient diagnostic resolution, it can become quite challenging for the analyst to determine the failure mechanism in an efficient and effective way. Fault isolation could be performed in combination with the diagnosis results but there are cases with mismatch between the results (location, fault type, suspect nets). When the diagnostic resolution is low, the probability for such mismatches are high. This paper proposes an approach to increase the diagnostic resolution by utilizing a high-resolution targeted pattern (HRT) and single shot logic (SSL) patterns. Two cases will be discussed in the paper to highlight this approach and show in detail how it was utilized on actual failing units.","PeriodicalId":188323,"journal":{"name":"ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132684439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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