Highly linear high isolation SPDT switch IC with back-gate effect and floating body technique in 180-nm CMOS

Abstract

This paper presents a broadband single-pole double-throw (SPDT) switch IC in a 180-nm CMOS process. Back-gate voltage injection and floating body technique are utilized to improve the power handling capability, insertion loss and isolation performance, simultaneously. The fabricated SPDT switch IC has exhibited an input referred 0.3-dB compression point of 21.0 dBm, an isolation of 42.7 dB and an insertion loss of 1.1 dB for transmit mode at an operation frequency of 5.0 GHz.