A digital background calibration technique for split DAC based SAR ADC by using redundant cycle

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406952

Wuguang Wang, R. Huang, Guoquan Sun, Weijun Mao, Xiaolei Zhu

引用次数: 3

Abstract

A digital background calibration technique for split CDAC mismatch is proposed. It uses the dummy capacitor to generate an extra calibration bit. The mismatch of the CDAC array is detected by the calibration bit and fed back to the compensation capacitor. A 9b 100MS/s SAR ADC is demonstrated in standard 65nm CMOS technology. Simulation results show that the DNL and INL can be decreased to ±0.1 LSB and +0.11/-0.13 LSB, respectively, after using this technique. The proposed calibration block consumes only 50μw from a 1.2V supply.

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基于冗余周期的分割DAC型SAR ADC数字背景标定技术

提出了一种分路CDAC失配数字背景标定技术。它使用假电容来产生一个额外的校准位。CDAC阵列的失配由校准位检测并反馈给补偿电容。在标准的65nm CMOS技术下演示了9b 100MS/s SAR ADC。仿真结果表明，采用该技术后，DNL和INL分别可降至±0.1 LSB和+0.11/-0.13 LSB。所提出的校准块仅消耗50μw的1.2V电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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