Grep: Performance Enhancement in MultiCore Processors using an Adaptive Graph Prefetcher

Abstract

Memory latency and off-chip bandwidth have been struggling to keep up with computing performance in modern computer systems. In this regard, prefetching helps in masking the long memory access latency at various cache levels by continuously monitoring an application’s memory access pattern. Upon detecting a pattern, it prefetches cache block ahead of its use. However, complex patterns such as directed or indirected pointer access, linked lists, and so on does not adhere to any specific pattern and hence, makes prefetching impossible. The paper proposes Grep, an adaptive graph based data prefetcher that monitors L1D cache misses and prefetches block in L2 cache. Unlike state-of-the-art prefetchers, Grep does not search for patterns in the miss stream. Rather, it generates a predecessor-successor relationship among the cache misses by constructing an occurrence graph that stores the frequency and sequence of subsequent cache block accesses. Therefore, both regular and irregular patterns in the miss stream can be predicted. Upon an address match in the occurrence graph, Grep prefetches block with a confidence value. Experimentally, it improves prefetch coverage and accuracy by 35.5% and 18.8%, respectively, compared to SPP.