Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing

R. Lea
{"title":"Wafer-scale massively parallel computing modules for fault-tolerant signal and data processing","authors":"R. Lea","doi":"10.1109/DFTVS.1991.199940","DOIUrl":null,"url":null,"abstract":"A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme.<<ETX>>","PeriodicalId":440536,"journal":{"name":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1991.199940","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

A WASP device is a WSI implementation of an ASP (Associative String Processor) substring and, as such, it constitutes a fundamental building block for the assembly of SIMD Massively Parallel Computer (MPC) components. This paper describes current progress in the WASP 3/4/5 programme.<>
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
用于容错信号和数据处理的晶圆级大规模并行计算模块
WASP设备是ASP(关联字符串处理器)子串的WSI实现,因此,它构成了SIMD大规模并行计算机(MPC)组件组装的基本构建块。本文描述了WASP 3/4/5计划的最新进展。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Current-mode techniques for analog VLSI: technology and defect tolerance issues Effects of fault tolerance on the reliability of memory array supports Reliability evaluation of FUSS and other reconfiguration schemes Circuit design for a large area high-performance crossbar switch Delay fault simulation of self-checking error checkers
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1