W. Chakraborty, Uma Sharma, S. Datta, S. Mahapatra
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引用次数: 4
Abstract
28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (VG/VD) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔVT) into interface trap generation due to pure HCD (ΔVIT-HC), Bias Temperature Instability (BTI, ΔVIT-BT), and electron/hole trapping (ΔVET/ΔVHT) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.
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