{"title":"A compiler design for IEC 1131-3 standard languages of programmable logic controllers","authors":"H. Kim, Jae Young Lee, W. Kwon","doi":"10.1109/SICE.1999.788715","DOIUrl":null,"url":null,"abstract":"This paper proposes a compiler design for IEC 1131-3 standard languages of PLCs (programmable logic controllers). It describes the structure of the front end of the compiler and the optimization phase of the intermediate representation of the back end. The paper also proposes optimization methods using several characteristics of the PLC. A software-based optimization uses the flow of the program and a hardware-based optimization is implemented by a programmable logic device to accelerate the logical operations that are most part of the PLC instructions. A benchmark test shows the proposed compiler speeds up the execution of the PLC.","PeriodicalId":103164,"journal":{"name":"SICE '99. Proceedings of the 38th SICE Annual Conference. International Session Papers (IEEE Cat. No.99TH8456)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"SICE '99. Proceedings of the 38th SICE Annual Conference. International Session Papers (IEEE Cat. No.99TH8456)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SICE.1999.788715","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper proposes a compiler design for IEC 1131-3 standard languages of PLCs (programmable logic controllers). It describes the structure of the front end of the compiler and the optimization phase of the intermediate representation of the back end. The paper also proposes optimization methods using several characteristics of the PLC. A software-based optimization uses the flow of the program and a hardware-based optimization is implemented by a programmable logic device to accelerate the logical operations that are most part of the PLC instructions. A benchmark test shows the proposed compiler speeds up the execution of the PLC.
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