A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406934

Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim

引用次数: 3

Abstract

A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).

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一个9位，110毫秒/秒的流水线sar ADC，采用时间交错技术和共享比较器

提出了一种9位110毫秒/秒的流水线式sar ADC。为了减轻转换率和功耗之间的设计权衡，该设计采用了电压型开环放大器和具有比较器共享的时交错SAR架构。采用65nm CMOS技术仿真的ADC在110MS/s的采样率下，在Nyquist输入频率附近实现了8.63位的ENOB。功率消耗为7.9mW，产生181.3fJ/ FoM转换步长。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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