Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology

Abstract

A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.