Novel scalable TDDB model for large-area MIM decoupling capacitors in high performance LSIs

Abstract

Scalable TDDB model for large-area MIM capacitors is proposed to guarantee the reliability, limited by the defect-related extrinsic failure mode. Analysis based on this model leads to the guideline for the MIM design such as the dielectric thickness and capacitor area to achieve lifetime required for large decoupling capacitance on high-performance processors. Proposing TDDB model reveals that highly reliable MIM capacitor with ≫30 mm2, or ≫200 nF, per chip is realized successfully, suppressing the dynamic power-line noise in high performance LSIs.