Novel ECC structure and evaluation method for NAND flash memory

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406921

Jiang Xiao-bo, Tang Xue-qing, Huang Wei-pei

引用次数: 7

Abstract

The evaluation of error correction code (ECC) for NAND flash memory is increasingly complicated by the increasing bit error rate in memory. The concept of error-free information capacity is proposed to evaluate the performance ECC of NAND flash memory. The new method simultaneously considers the capacity and reliability of NAND flash memory. Low-density parity-check (LDPC) codes with a medium code rate can improve the integrated performance of NAND flash memory in order of magnitudes. Observations provide guides for the development of ECC schemes in NAND flash memory in future. An ECC structure based on adaptive LDPC codes is also presented in this paper. The new structure achieves integrated performance of both capacity and reliability in NAND flash memory.

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NAND快闪记忆体的新型ECC结构与评估方法

随着内存误码率的不断提高，NAND闪存的纠错码评估变得越来越复杂。提出了无差错信息容量的概念来评价NAND闪存的ECC性能。该方法同时考虑了NAND闪存的容量和可靠性。具有中等码率的低密度奇偶校验码(LDPC)可以将NAND闪存的集成性能提高数个数量级。观察结果为未来NAND闪存中ECC方案的发展提供了指导。本文还提出了一种基于自适应LDPC码的ECC结构。新结构实现了NAND闪存容量和可靠性的综合性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2015 28th IEEE International System-on-Chip Conference (SOCC)

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