CAPSL: The Component Authentication Process for Sandboxed Layouts

Taylor J. L. Whitaker, C. Bobda
{"title":"CAPSL: The Component Authentication Process for Sandboxed Layouts","authors":"Taylor J. L. Whitaker, C. Bobda","doi":"10.1109/ISVLSI.2017.78","DOIUrl":null,"url":null,"abstract":"In this work, we propose a system-on-chip (SoC) design tool for the automatic generation of hardware sandboxes for securing untrusted IP to be integrated into trusted systems. The Component Authentication Process for Sandboxed Layouts (CAPSL) is a design flow that incorporates behavioral specifications of IP interfaces in order to generate sandboxes purposed for detecting trojan activation and isolating possible damage to a system at run-time. CAPSL adopts two formal models, interface automata and the Property Specification Language's sequential extended regular expressions (SERE), to generate reference monitors governing interactions of a collection of non-trusted IP. The sandbox partitions an untrusted sector that includes the non-secure IP and appropriate virtualized resources and controllers to isolate sandbox-system interactions upon deviation from the behavioral checkers. We review our design flow with an analysis of behavioral policy versatility and detection and defense mechanisms employed for various Trust-Hub.org benchmarks. Also presented is a brief resource evaluation highlighting CAPSL's reduced overhead compared to other run-time verification techniques.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2017.78","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In this work, we propose a system-on-chip (SoC) design tool for the automatic generation of hardware sandboxes for securing untrusted IP to be integrated into trusted systems. The Component Authentication Process for Sandboxed Layouts (CAPSL) is a design flow that incorporates behavioral specifications of IP interfaces in order to generate sandboxes purposed for detecting trojan activation and isolating possible damage to a system at run-time. CAPSL adopts two formal models, interface automata and the Property Specification Language's sequential extended regular expressions (SERE), to generate reference monitors governing interactions of a collection of non-trusted IP. The sandbox partitions an untrusted sector that includes the non-secure IP and appropriate virtualized resources and controllers to isolate sandbox-system interactions upon deviation from the behavioral checkers. We review our design flow with an analysis of behavioral policy versatility and detection and defense mechanisms employed for various Trust-Hub.org benchmarks. Also presented is a brief resource evaluation highlighting CAPSL's reduced overhead compared to other run-time verification techniques.
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CAPSL:沙盒布局的组件认证过程
在这项工作中,我们提出了一个系统级芯片(SoC)设计工具,用于自动生成硬件沙箱,以确保不受信任的IP集成到受信任的系统中。沙盒布局的组件认证过程(CAPSL)是一个设计流程,它结合了IP接口的行为规范,以便生成沙盒,用于检测木马激活并在运行时隔离可能对系统造成的损害。CAPSL采用两个正式模型,接口自动机和属性规范语言的顺序扩展正则表达式(SERE),以生成控制非可信IP集合交互的参考监视器。沙盒将不受信任的扇区进行分区,其中包括不安全的IP和适当的虚拟化资源和控制器,以便在偏离行为检查器时隔离沙盒系统交互。我们通过对各种Trust-Hub.org基准测试使用的行为策略通用性和检测和防御机制的分析来审查我们的设计流程。此外,还简要介绍了与其他运行时验证技术相比,CAPSL减少了开销的资源评估。
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