Lakshmi Bhamidipati, B. Gunna, H. Homayoun, Avesta Sasan
This paper, presents a novel technique for reducing the intensity of IR hot-spots by leveraging the unused timing slacks to schedule useful skews. The peak current minimization problem is reformulated into a collection of smaller problems of reducing the peak current of each via-stack in the on-chip Power Delivery Network (PDN). In addition to timing information, it considers the PDN and cell placement information while scheduling the clock arrival times. Hence, while reducing the peak current, it effectively reduces the intensity the IR hot- spots. Application of the proposed solution to a selected number of IWLS benchmarks reduces the peak IR-drop by ±35%, and peak current by ±37%.
{"title":"A Power Delivery Network and Cell Placement Aware IR-Drop Mitigation Technique: Harvesting Unused Timing Slacks to Schedule Useful Skews","authors":"Lakshmi Bhamidipati, B. Gunna, H. Homayoun, Avesta Sasan","doi":"10.1109/ISVLSI.2017.55","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.55","url":null,"abstract":"This paper, presents a novel technique for reducing the intensity of IR hot-spots by leveraging the unused timing slacks to schedule useful skews. The peak current minimization problem is reformulated into a collection of smaller problems of reducing the peak current of each via-stack in the on-chip Power Delivery Network (PDN). In addition to timing information, it considers the PDN and cell placement information while scheduling the clock arrival times. Hence, while reducing the peak current, it effectively reduces the intensity the IR hot- spots. Application of the proposed solution to a selected number of IWLS benchmarks reduces the peak IR-drop by ±35%, and peak current by ±37%.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133351044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shvan Karim, J. Harkin, L. McDaid, B. Gardiner, Junxiu Liu, D. Halliday, A. Tyrrell, J. Timmis, Alan G. Millard, Anju P. Johnson
This paper presents a hardware based implementation of a biologically-faithful astrocyte-based selfrepairing mechanism for Spiking Neural Networks. Spiking Astrocyte-neuron Networks (SANNs) are a new computing paradigm which capture the key mechanisms of how the human brain performs repairs. Using SANN in hardware affords the potential for realizing computing architecture that can self-repair. This paper demonstrates that Spiking Astrocyte Neural Network (SANN) in hardware have a resilience to significant levels of faults. The key novelty of the paper resides in implementing an SANN on FPGAs using fixed-point representation and demonstrating graceful performance degradation to different levels of injected faults via its self-repair capability. A fixed-point implementation of astrocyte, neurons and tripartite synapses are presented and compared against previous hardware floating-point and Matlab software implementations of SANN. All results are obtained from the SANN FPGA implementation and show how the reduced fixedpoint representation can maintain the biologically-realistic repair capability
{"title":"Assessing Self-Repair on FPGAs with Biologically Realistic Astrocyte-Neuron Networks","authors":"Shvan Karim, J. Harkin, L. McDaid, B. Gardiner, Junxiu Liu, D. Halliday, A. Tyrrell, J. Timmis, Alan G. Millard, Anju P. Johnson","doi":"10.1109/ISVLSI.2017.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.80","url":null,"abstract":"This paper presents a hardware based implementation of a biologically-faithful astrocyte-based selfrepairing mechanism for Spiking Neural Networks. Spiking Astrocyte-neuron Networks (SANNs) are a new computing paradigm which capture the key mechanisms of how the human brain performs repairs. Using SANN in hardware affords the potential for realizing computing architecture that can self-repair. This paper demonstrates that Spiking Astrocyte Neural Network (SANN) in hardware have a resilience to significant levels of faults. The key novelty of the paper resides in implementing an SANN on FPGAs using fixed-point representation and demonstrating graceful performance degradation to different levels of injected faults via its self-repair capability. A fixed-point implementation of astrocyte, neurons and tripartite synapses are presented and compared against previous hardware floating-point and Matlab software implementations of SANN. All results are obtained from the SANN FPGA implementation and show how the reduced fixedpoint representation can maintain the biologically-realistic repair capability","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Konstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, S. Xydis, Tobias Becker, G. Gaydadjiev, D. Soudris
This paper presents the cloud infrastructure of the AEGLE project, that targets to integrate cloud technologies together with heterogeneous reconfigurable computing in large scale healthcare systems for Big Bio-Data analytics. AEGLEs engineering concept brings together the hot big-data engines with emerging acceleration technologies, putting the basis for personalized and integrated health-care services, while also promoting related research activities. We introduce the design of AEGLE’s accelerated infrastructure along with the corresponding software and hardware acceleration stacks to support various big data analytics workloads showing that through effective resource containerization AEGLE’s cloud infrastructure is able to support high heterogeneity regarding to storage types, execution engines, utilized tools and execution platforms. Special care is given to the integration of high performance accelerators within the overall software stack of AEGLE’s infrastructure, which enable efficient execution of analytics, up to 140× according to our preliminary evaluations, over pure software executions.
{"title":"AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics","authors":"Konstantina Koliogeorgi, Dimosthenis Masouros, Georgios Zervakis, S. Xydis, Tobias Becker, G. Gaydadjiev, D. Soudris","doi":"10.1109/ISVLSI.2017.70","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.70","url":null,"abstract":"This paper presents the cloud infrastructure of the AEGLE project, that targets to integrate cloud technologies together with heterogeneous reconfigurable computing in large scale healthcare systems for Big Bio-Data analytics. AEGLEs engineering concept brings together the hot big-data engines with emerging acceleration technologies, putting the basis for personalized and integrated health-care services, while also promoting related research activities. We introduce the design of AEGLE’s accelerated infrastructure along with the corresponding software and hardware acceleration stacks to support various big data analytics workloads showing that through effective resource containerization AEGLE’s cloud infrastructure is able to support high heterogeneity regarding to storage types, execution engines, utilized tools and execution platforms. Special care is given to the integration of high performance accelerators within the overall software stack of AEGLE’s infrastructure, which enable efficient execution of analytics, up to 140× according to our preliminary evaluations, over pure software executions.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131572647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM.
{"title":"On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC","authors":"Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, D. Kwai, Yung-Fa Chou","doi":"10.1109/ISVLSI.2017.86","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.86","url":null,"abstract":"In 3DIC design, we may face the problem in manufacturing faults of through silicon vias (TSVs) and microbumps, and it will cause insufficient power delivery and eventually result in fatal error of functioning. In this work, we propose a power TSV/microbump fault tolerance scheme to resolve this issue. First, we use a fast heuristic to predict the worst IR-drop distribution under a given faulty rate by analyzing power simulation results. Next, we use an incremental repair method to enhance power delivery network until reaching the given target IR-drop. The experimental results show that our methodology is effective in power delivery network enhancement in TSV/microbump DFM.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new technique of magnitudecomparator for quantum bit string comparison. In the proposedmethod, the comparison between two quantum bit strings isperformed with the optimum number of operations. We have alsoshown that the proposed technique has time complexityO(( + )), whereas the best known existing technique hasO(nlog n),where n is the number of quantum bits. In addition, wehave proposed another technique to produce a compact quantumcomparator circuit. We have also introduced three new quantumgates with unique unitary matrices which represent the proposedquantum circuit more compactly than the existing quantumgates. The proposed comparator circuit has been designed usingthe proposed quantum bit comparator circuit named MidpointQubits Comparison (MQC) Circuit and another proposedquantum bit comparator circuit named Rest Qubits Comparison(RQC) Circuit. The comparative study shows that the proposedcomparator circuit outperforms the existing comparators; e.g.,the proposed 64-qubit comparator improves 7.19% on number ofquantum gates, area and delay; and 50.39% on garbage outputsover the existing best one
{"title":"Area and Delay Efficient Design of a Quantum Bit String Comparator","authors":"H. Babu, Lafifa Jamal, S. V. Dibbo, A. Biswas","doi":"10.1109/ISVLSI.2017.130","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.130","url":null,"abstract":"This paper presents a new technique of magnitudecomparator for quantum bit string comparison. In the proposedmethod, the comparison between two quantum bit strings isperformed with the optimum number of operations. We have alsoshown that the proposed technique has time complexityO(( + )), whereas the best known existing technique hasO(nlog n),where n is the number of quantum bits. In addition, wehave proposed another technique to produce a compact quantumcomparator circuit. We have also introduced three new quantumgates with unique unitary matrices which represent the proposedquantum circuit more compactly than the existing quantumgates. The proposed comparator circuit has been designed usingthe proposed quantum bit comparator circuit named MidpointQubits Comparison (MQC) Circuit and another proposedquantum bit comparator circuit named Rest Qubits Comparison(RQC) Circuit. The comparative study shows that the proposedcomparator circuit outperforms the existing comparators; e.g.,the proposed 64-qubit comparator improves 7.19% on number ofquantum gates, area and delay; and 50.39% on garbage outputsover the existing best one","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124245459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sparsh Mittal, R. Bishnoi, Fabian Oboril, Haonan Wang, M. Tahoori, Adwait Jog, J. Vetter
With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.
{"title":"Architecting SOT-RAM Based GPU Register File","authors":"Sparsh Mittal, R. Bishnoi, Fabian Oboril, Haonan Wang, M. Tahoori, Adwait Jog, J. Vetter","doi":"10.1109/ISVLSI.2017.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.17","url":null,"abstract":"With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hua Fan, F. Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, H. Heidari
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC.
{"title":"Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC","authors":"Hua Fan, F. Maloberti, Dagang Li, Daqian Hu, Yuanjun Cen, H. Heidari","doi":"10.1109/ISVLSI.2017.97","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.97","url":null,"abstract":"This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mass production of secure circuits demands nowadays new testing methods able to detect the possible existence of hardware Trojans, which might be even a slight layout alteration. This paper proposes a new method for the detection of Trojans by exploiting preexisting current sensors that are originally built in system's subcircuits as online-testing devices for detecting radiation- or laser-induced transient currents. In the proposed method, the sensor operates as an offline-testing mechanism to provide digital signatures of the subcircuit's substrate after injection of current pulses into MOSFET body terminals. Simulation results considering process variations demonstrate the effectiveness of the method on detecting gate- and layout-level Trojans.
{"title":"Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors","authors":"Leonel Acunha Guimaraes, R. P. Bastos, L. Fesquet","doi":"10.1109/ISVLSI.2017.58","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.58","url":null,"abstract":"The mass production of secure circuits demands nowadays new testing methods able to detect the possible existence of hardware Trojans, which might be even a slight layout alteration. This paper proposes a new method for the detection of Trojans by exploiting preexisting current sensors that are originally built in system's subcircuits as online-testing devices for detecting radiation- or laser-induced transient currents. In the proposed method, the sensor operates as an offline-testing mechanism to provide digital signatures of the subcircuit's substrate after injection of current pulses into MOSFET body terminals. Simulation results considering process variations demonstrate the effectiveness of the method on detecting gate- and layout-level Trojans.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133074209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.
{"title":"A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes","authors":"Saleh Usman, Mohammad M. Mansour, A. Chehab","doi":"10.1109/ISVLSI.2017.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.42","url":null,"abstract":"This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128100127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede
Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.
{"title":"STBC: Side Channel Attack Tolerant Balanced Circuit with Reduced Propagation Delay","authors":"Hyunmin Kim, Seokhie Hong, B. Preneel, I. Verbauwhede","doi":"10.1109/ISVLSI.2017.22","DOIUrl":"https://doi.org/10.1109/ISVLSI.2017.22","url":null,"abstract":"Side channel attacks exploit the physical properties of integrated circuits to extract sensitive information. They are becoming increasingly important in the context of the deployment of the Internet of Things. One of the most effective countermeasures consists of modifying the logic circuits to reduce the leakage through side channels. This paper presents a novel side channel attack tolerant balanced circuit (STBC) based on a dynamic and differential configuration. Its main feature is the use of an improved binary decision diagram (BDD) with a multi-output function and internal gate sharing to reduce the implementation area. Compared to the earlier proposed dual-rail pre-charge circuit with binary decision diagram (DP-BDD) technique, an area reduction of 13.7% is achieved. A fixed versus random t-test shows that STBC obtains a substantial reduction in information leakage even though small peak exists. Further, its input variable dependence is comparable with that of a normal CMOS circuit and similar with DP-BDD.","PeriodicalId":187936,"journal":{"name":"2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"819 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130827676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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