{"title":"Does the floorplan of a chip affect its yield?","authors":"Z. Koren, I. Koren","doi":"10.1109/DFTVS.1993.595754","DOIUrl":null,"url":null,"abstract":"The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip.","PeriodicalId":213798,"journal":{"name":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFTVS.1993.595754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The floorplan of a VLSI chip and its projected yield are usually considered to be completely unrelated issues. This commonly used assumption does not necessarily hold for several recently designed VLSI chips that incorporate some defect tolerance. The purpose of this work is to investigate the relationship between floorplanning and yield for this type of chip.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
