Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution

Abstract

In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest voltage (>30V) during NAND Flash programming [1]-[2]. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BVDSS) from virgin state is usually lower than that after stress, which is called the "walk-out" effect [3]-[4]. The walk-out effect can be recovered by a high-temperature baking, indicating it’s not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect [5]-[6]. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BVDSS with acceptable transistor performances.