N. Suematsu, O. Wada, S. Kameda, T. Takagi, K. Tsubouchi
{"title":"A 0.8–1.9GHz-band CMOS direct digital RF quadrature modulator","authors":"N. Suematsu, O. Wada, S. Kameda, T. Takagi, K. Tsubouchi","doi":"10.1109/RFIT.2015.7377916","DOIUrl":null,"url":null,"abstract":"A 0.8-1.9 GHz direct digital radio frequency (RF) quadrature modulator is designed and fabricated in 90 nm CMOS process. The bit number and the CLK frequency of I/Q digital input signals are designed to satisfy the required EVM, ACPR/NACPR and system bandwidth for 0.9/1.9GHz W-CDMA terminals. The fabricated quadrature modulator performs EVM of less than -22.7dB, ACP/NACP of less than -36.1dBc and spurious free range of 197MHz (wider than the W-CDMA system bandwidth of 60MHz) with 8-bit, 100Msps I/Q digital input signals and the d.c. power consumption of 10mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377916","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 0.8-1.9 GHz direct digital radio frequency (RF) quadrature modulator is designed and fabricated in 90 nm CMOS process. The bit number and the CLK frequency of I/Q digital input signals are designed to satisfy the required EVM, ACPR/NACPR and system bandwidth for 0.9/1.9GHz W-CDMA terminals. The fabricated quadrature modulator performs EVM of less than -22.7dB, ACP/NACP of less than -36.1dBc and spurious free range of 197MHz (wider than the W-CDMA system bandwidth of 60MHz) with 8-bit, 100Msps I/Q digital input signals and the d.c. power consumption of 10mW.