A two-phase reconfiguration strategy for extracting linear arrays out of two-dimensional architectures

Abstract

In order to maintain constant interconnection wire lengths between logically adjacent cells and avoid introducing additional tracks of buses and switches when linear arrays are extracted out of two-dimensional architectures with faulty processing elements, the spiral reconfiguration approach has been introduced. Its main drawback, relative to the tree and patching approaches, is that it leads to low harvesting. The authors introduce a two-phase reconfiguration strategy that drastically increases the harvesting ratio. The algorithm of the first phase achieves comparable harvesting to the previously proposed schemes, while it is simpler and can be implemented by on-chip logic. The algorithm of the second phase may complement any other scheme used during the first phase, and raises the harvesting ratio to levels that could be achieved by the much more involved tree approach.