Impact of High-k spacer and Negative Capacitance on Double Gate Junctionless Transistor for Improved Short Channel Immunity and Reliability

Abstract

In the present work, the impact of high-k spacers and Negative Capacitance (NC) has been examined on the performance of nanoscale Double Gate Junctionless Transistors by self consistently solving Landau Khalatnikov equation with TCAD simulations. Ferroelectric hafnium oxide is considered in gate stack with interfacial layer of silicon dioxide. The impact of different dielectric constants of spacer and different spacer lengths have been explored extensively on various electrical parameters. It has been demonstrated that high-k spacers significantly improve the gate controllability, thereby, further enhancing the negative capacitance (NC) effect of ferroelectric layer on device operation. The subthreshold swing values as low as 10mV/dec have been obtained along with substantial improvement in Ion/Ioff ratio (about 3 orders), thereby, indicating suitability of the device for future ultra low power electronic applications.