Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study

IEEE International SOC Conference, 2004. Proceedings. Pub Date : 2004-11-30 DOI:10.1109/SOCC.2004.1362384

H. Fredriksson, C. Svensson

引用次数: 4

Abstract

A decision feedback equalizer (DFE), well suited for implementation in standard CMOS and capable of recovering data sent over a multi-drop memory bus at several Gb/s per wire, is presented. The structure features low latency and permits easy switching of filter coefficient sets, which enables the bus host to receive data from different slaves. Results from near-hardware simulations of 3 Gb/s per wire transmissions over a four tap standard DDR memory bus are presented.

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多滴，gb/s，存储总线的混合信号DFE -可行性研究

提出了一种决策反馈均衡器(DFE)，非常适合在标准CMOS中实现，能够恢复在多滴存储器总线上以每根线数Gb/s的速度发送的数据。该结构具有低延迟的特点，并且允许滤波器系数集的轻松切换，这使得总线主机能够接收来自不同slave的数据。给出了在四分路标准DDR存储器总线上每线传输3gb /s的近硬件仿真结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE International SOC Conference, 2004. Proceedings.

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