Ultra-low resistance W/Si/sub 1-x/Ge/sub x//Si source-drain contacts

Abstract

Fabrication of CMOS devices with feature sizes on the order of 100 nm will require junction depths of less than 70 nm in order to control short-channel effects. Fully-scaled 100x100 nm/sup 2/ source-drain regions in such devices will require contact resistivities of less than 10/sup -7/ ohm-cm/sup 2/ in order not to reach limits on currents. A W contact technology was been pursued in this work. W can be be deposited selectively with little substrate consumption and it has been shown to have a low contact resistivity on n+ Si. Si/sub x/Ge/sub 1-x/ has the further potential advantage of lowered tunnel barrier heights to p+ Si because of the reduced bandgap. Therefore there is a possibility for improving contact resistivities to p+ Si as well. Finally, W is an excellent barrier metal with good thermal stability both for Si and Si/sub x/Ge/sub 1-x/.