The relation between light emitting characteristics and the porous silicon microstructure has been analyzed by applying a new in situ electroluminescence and photoluminescence spectra measurement technique during anodic oxidation. On the basis of this result, a porous silicon structure has been modified to improve /spl nu/ (the external light emission efficiency), and a maximum /spl nu/ of 0.35%, the highest confirmed value ever reported, has been obtained.
{"title":"Improvement of porous silicon EL efficiency during anodic oxidation and the application of a new microstructure analysis method","authors":"T. Sakai, T. Suzuki, Li Zhang","doi":"10.1109/DRC.1995.496301","DOIUrl":"https://doi.org/10.1109/DRC.1995.496301","url":null,"abstract":"The relation between light emitting characteristics and the porous silicon microstructure has been analyzed by applying a new in situ electroluminescence and photoluminescence spectra measurement technique during anodic oxidation. On the basis of this result, a porous silicon structure has been modified to improve /spl nu/ (the external light emission efficiency), and a maximum /spl nu/ of 0.35%, the highest confirmed value ever reported, has been obtained.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have demonstrated broad range continuous wavelength tuning as wide as 31 nm in a resonant cavity light emitter using a Au/SiN/sub x/H/sub y/ deformable-membrane top mirror. Further linewidth reduction was achieved by employing a higher-reflectivity DBR membrane.
{"title":"Broadly-tunable, narrow-linewidth resonant cavity light emitter","authors":"M. Larson, J. Harris","doi":"10.1109/DRC.1995.496299","DOIUrl":"https://doi.org/10.1109/DRC.1995.496299","url":null,"abstract":"We have demonstrated broad range continuous wavelength tuning as wide as 31 nm in a resonant cavity light emitter using a Au/SiN/sub x/H/sub y/ deformable-membrane top mirror. Further linewidth reduction was achieved by employing a higher-reflectivity DBR membrane.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124866845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R.B. Hulfachor, K.W. Kim, M. Littlejohn, C. Osburn
To investigate hot carrier phenomena in 0.1 /spl mu/m n-MOSFETs under low-voltage conditions, we employ a comprehensive Monte Carlo simulator to compare hot electron injection into the oxide for a variety of drain and channel design strategies. Pertinent features of the Monte Carlo simulator include: (1) electron-electron scattering, which is significant in producing the high energy tail in the electron energy distribution; (2) an enhanced particle statistics algorithm to provide detail in the high energy tail; and (3) a coupled two-dimensional numerical solution to Poisson's equation that is rapidly recalculated every 0.1 fs to provide a self-consistent, dynamic electric field distribution. In addition, we examine relative device reliability in the variety of 0.1 /spl mu/m designs by first combining hot electron injection distributions provided by Monte Carlo simulations with an empirical model to generate interface state distributions and next incorporating these interface states into SPISCES to calculate induced changes in device characteristics.
{"title":"A Monte Carlo study of drain and channel engineering effects on hot electron injection and induced device degradation in 0.1 /spl mu/m n-MOSFETs","authors":"R.B. Hulfachor, K.W. Kim, M. Littlejohn, C. Osburn","doi":"10.1109/DRC.1995.496229","DOIUrl":"https://doi.org/10.1109/DRC.1995.496229","url":null,"abstract":"To investigate hot carrier phenomena in 0.1 /spl mu/m n-MOSFETs under low-voltage conditions, we employ a comprehensive Monte Carlo simulator to compare hot electron injection into the oxide for a variety of drain and channel design strategies. Pertinent features of the Monte Carlo simulator include: (1) electron-electron scattering, which is significant in producing the high energy tail in the electron energy distribution; (2) an enhanced particle statistics algorithm to provide detail in the high energy tail; and (3) a coupled two-dimensional numerical solution to Poisson's equation that is rapidly recalculated every 0.1 fs to provide a self-consistent, dynamic electric field distribution. In addition, we examine relative device reliability in the variety of 0.1 /spl mu/m designs by first combining hot electron injection distributions provided by Monte Carlo simulations with an empirical model to generate interface state distributions and next incorporating these interface states into SPISCES to calculate induced changes in device characteristics.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123407366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, normal incident intersubband absorption has been observed using InGaAs based quantum well structures. In this abstract, we report the first demonstration of a normal incident infrared detector using n-type In/sub x/Ga/sub 1-x/As/GaAs multiple quantum wells.
{"title":"Normal incident intersubband infrared detector using n-type InGaAs/GaAs quantum wells","authors":"G. Karunasiri, R. Shih, J. Chen","doi":"10.1109/DRC.1995.496296","DOIUrl":"https://doi.org/10.1109/DRC.1995.496296","url":null,"abstract":"Recently, normal incident intersubband absorption has been observed using InGaAs based quantum well structures. In this abstract, we report the first demonstration of a normal incident infrared detector using n-type In/sub x/Ga/sub 1-x/As/GaAs multiple quantum wells.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The dominant silicon devices used in ULSI (Ultra Large Scale Integration) are considered likely to be CMOS (Complementary Metal Oxide Semiconductor) devices, except for dc limited areas in, which bipolar devices may survive, Even high performance CPUs (Central Processing Units) of mainframe computers are going to be replaced by CMOS, because CMOS devices can meet severe requirements for power reduction, performance improvement and cost reduction, while maintaining a high integration capability. However, CMOS devices are not perfect, and performance improvements are constrained by several physical phenomena such as the short-channel-effects, carrier velocity saturation, and resistance/capacitance increase. We perform CMOS-device performance evaluation using an analytical model, in which carrier velocity saturation, diffusion-layer resistance and capacitance, and mobility degradation etc. are taken into consideration, This analysis suggests what the device structures should be. Then, several measures necessary for performance improvements are described, and finally characteristics of the fabricated CMOS devices are introduced.
{"title":"Guidelines for high-performance CMOS-devices development","authors":"S. Kimura","doi":"10.1109/DRC.1995.496224","DOIUrl":"https://doi.org/10.1109/DRC.1995.496224","url":null,"abstract":"The dominant silicon devices used in ULSI (Ultra Large Scale Integration) are considered likely to be CMOS (Complementary Metal Oxide Semiconductor) devices, except for dc limited areas in, which bipolar devices may survive, Even high performance CPUs (Central Processing Units) of mainframe computers are going to be replaced by CMOS, because CMOS devices can meet severe requirements for power reduction, performance improvement and cost reduction, while maintaining a high integration capability. However, CMOS devices are not perfect, and performance improvements are constrained by several physical phenomena such as the short-channel-effects, carrier velocity saturation, and resistance/capacitance increase. We perform CMOS-device performance evaluation using an analytical model, in which carrier velocity saturation, diffusion-layer resistance and capacitance, and mobility degradation etc. are taken into consideration, This analysis suggests what the device structures should be. Then, several measures necessary for performance improvements are described, and finally characteristics of the fabricated CMOS devices are introduced.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122468741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A unique phenomenon that we have observed in all advanced bipolar transistors operating below liquid-nitrogen temperature (LNT=77.3K) is the development of a nonideal collector current at very low injection levels. A trap-assisted tunneling of carriers from the emitter to the collector through the base potential barrier is suggested as the mechanism responsible for this observed phenomenon. The differences in the temperature dependence of the collector leakage current between SiGe HBTs and Si BJTs is explained by modelling the electron tunneling transition probability from the emitter region to traps located in the neutral-base using SCORPIO, a calibrated 1-D simulator for low-temperature Si/SiGe bipolar transistors. A self-aligned, shallow- and deep-trench isolated, epitaxial-base transistor with a polysilicon emitter contact was used in the present investigation.
{"title":"Novel collector current phenomenon in advanced bipolar transistors operated at deep cryogenic temperatures","authors":"A. Joseph, J. Cressler, D. M. Richey","doi":"10.1109/DRC.1995.496312","DOIUrl":"https://doi.org/10.1109/DRC.1995.496312","url":null,"abstract":"A unique phenomenon that we have observed in all advanced bipolar transistors operating below liquid-nitrogen temperature (LNT=77.3K) is the development of a nonideal collector current at very low injection levels. A trap-assisted tunneling of carriers from the emitter to the collector through the base potential barrier is suggested as the mechanism responsible for this observed phenomenon. The differences in the temperature dependence of the collector leakage current between SiGe HBTs and Si BJTs is explained by modelling the electron tunneling transition probability from the emitter region to traps located in the neutral-base using SCORPIO, a calibrated 1-D simulator for low-temperature Si/SiGe bipolar transistors. A self-aligned, shallow- and deep-trench isolated, epitaxial-base transistor with a polysilicon emitter contact was used in the present investigation.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121296159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Presents new experimental data and simulations of AlGaAs/InGaAs/GaAs two dimensional MESFETs (2D MESFETs) which utilize sidewall Schottky contacts on either side of a very narrow 2D electron gas channel. These devices demonstrate excellent scaling characteristics down to submicron dimensions in both the channel length and the width, which are attributed to the special geometry of the 2D-3D contacts suppressing both the narrow channel effect (NCE) and the drain induced barrier lowering (DIBL). Specifically, when the device was scaled from 1.0/spl times/1.0 /spl mu/m/sup 2/ to 0.8/spl times/0.5 /spl mu/m/sup 2/, output conductance was reduced from 40 mS/mm to less than 1 mS/mm, knee voltage was reduced from 0.75 V to 0.25 V, and the ideality factor was reduced from 1.3 to 1.08, while the threshold voltage became less negative from -0.5 V to 0.3 V as expected. An excellent source-drain breakdown voltage over 10 V, and a current ON/OFF ratio over 105 were also observed. The gate leakage current remains small up to 0.6 V gate bias, demonstrating a good Schottky barrier between the side gates and the 2D electron gas. These characteristics compare favorably with those of a conventional HFET with similar dimensions.
{"title":"Scaling of two dimensional MESFETs for ultra low power applications","authors":"W. Peatman, M. Hurt, H. Park, R. Tsai, M. Shur","doi":"10.1109/DRC.1995.496236","DOIUrl":"https://doi.org/10.1109/DRC.1995.496236","url":null,"abstract":"Presents new experimental data and simulations of AlGaAs/InGaAs/GaAs two dimensional MESFETs (2D MESFETs) which utilize sidewall Schottky contacts on either side of a very narrow 2D electron gas channel. These devices demonstrate excellent scaling characteristics down to submicron dimensions in both the channel length and the width, which are attributed to the special geometry of the 2D-3D contacts suppressing both the narrow channel effect (NCE) and the drain induced barrier lowering (DIBL). Specifically, when the device was scaled from 1.0/spl times/1.0 /spl mu/m/sup 2/ to 0.8/spl times/0.5 /spl mu/m/sup 2/, output conductance was reduced from 40 mS/mm to less than 1 mS/mm, knee voltage was reduced from 0.75 V to 0.25 V, and the ideality factor was reduced from 1.3 to 1.08, while the threshold voltage became less negative from -0.5 V to 0.3 V as expected. An excellent source-drain breakdown voltage over 10 V, and a current ON/OFF ratio over 105 were also observed. The gate leakage current remains small up to 0.6 V gate bias, demonstrating a good Schottky barrier between the side gates and the 2D electron gas. These characteristics compare favorably with those of a conventional HFET with similar dimensions.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"31 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134550197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Kapser, P. Deimel, W. Platz, U. Prechtel, W. Cabanski, H. Maier
Platinum silicide Schottky barrier detectors are widely used for infrared applications in the 3-5 /spl mu/m wavelength region. The uniformity of the metal deposition along with the compatibility of the fabrication process with standard CMOS technology makes PtSi highly suited for large and high resolution focal plane arrays. To improve the quantum efficiency we have fabricated PtSi Schottky diodes on p-Si with various dry-etched lamellar gratings. The grating periods were 3 /spl mu/m, 4 /spl mu/m and 5 /spl mu/m, and the grating amplitudes were chosen between 300 nm and 1100 nm. The grating structure influences the optical properties of the diode and the absorption in the PtSi layer depends on the polarization of the incoming radiation. For TE-polarized light the E-field vector is parallel to the grating grooves, for the TM-polarization it is perpendicular.
{"title":"Platinum silicide Schottky barrier infrared photodetectors with a grating: optical response and backbias-dependent polarization sensitivity","authors":"K. Kapser, P. Deimel, W. Platz, U. Prechtel, W. Cabanski, H. Maier","doi":"10.1109/DRC.1995.496273","DOIUrl":"https://doi.org/10.1109/DRC.1995.496273","url":null,"abstract":"Platinum silicide Schottky barrier detectors are widely used for infrared applications in the 3-5 /spl mu/m wavelength region. The uniformity of the metal deposition along with the compatibility of the fabrication process with standard CMOS technology makes PtSi highly suited for large and high resolution focal plane arrays. To improve the quantum efficiency we have fabricated PtSi Schottky diodes on p-Si with various dry-etched lamellar gratings. The grating periods were 3 /spl mu/m, 4 /spl mu/m and 5 /spl mu/m, and the grating amplitudes were chosen between 300 nm and 1100 nm. The grating structure influences the optical properties of the diode and the absorption in the PtSi layer depends on the polarization of the incoming radiation. For TE-polarized light the E-field vector is parallel to the grating grooves, for the TM-polarization it is perpendicular.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114526429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Mishkevich, A. Jordan, V. Swaminathan, J. Geary
InGaAsP/InP lasers operating at 1.3/spl mu/m and 1.55/spl mu/m wavelength are used currently in many long haul and local loop communication systems. In addition to demands on the performance characteristics of these lasers, their long-term reliability under the operating conditions should also be satisfactory. Strain is one of many factors that can affect laser reliability. The principal objective of the current work is to construct processing related thermal stresses in InP based laser structures.
{"title":"Finite element stress modeling of InGaAsP/InP lasers","authors":"V. Mishkevich, A. Jordan, V. Swaminathan, J. Geary","doi":"10.1109/DRC.1995.496307","DOIUrl":"https://doi.org/10.1109/DRC.1995.496307","url":null,"abstract":"InGaAsP/InP lasers operating at 1.3/spl mu/m and 1.55/spl mu/m wavelength are used currently in many long haul and local loop communication systems. In addition to demands on the performance characteristics of these lasers, their long-term reliability under the operating conditions should also be satisfactory. Strain is one of many factors that can affect laser reliability. The principal objective of the current work is to construct processing related thermal stresses in InP based laser structures.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129928574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Ho, R.A. Johnson, C.E. Chang, W. Ho, D. Pehlke, P. Zampardi, M. Chang, P. Asbeck
In this paper we present a novel technique which can significantly reduce the base-collector capacitance (C/sub bc/) in AlGaAs/GaAs HBTs. C/sub bc/, is a key limiter of HBT microwave gain and bandwidth. Our process uses high dose, high-energy ion implantation through the external base layer to compensate part of the heavily doped sub-collector. It also uses the more conventional self-aligned shallow implant to compensate the entire collector underneath the base contact. The total C/sub bc/ of the double implanted HBTs has been reduced by more than 35% with this new technique as compared to devices with shallow implant only. Under proper conditions, the double implantation produces little damage to the base (which can cause an increase in base resistance R/sub B/); thus the RF performance can be significantly improved. An f/sub MAX/ greater than 200 GHz has been obtained, comparable to the best previous reported results in common emitter HBTs.
{"title":"Base-collector capacitance reduction of AlGaAs/GaAs heterojunction bipolar transistors by deep ion implantation","authors":"M. Ho, R.A. Johnson, C.E. Chang, W. Ho, D. Pehlke, P. Zampardi, M. Chang, P. Asbeck","doi":"10.1109/DRC.1995.496282","DOIUrl":"https://doi.org/10.1109/DRC.1995.496282","url":null,"abstract":"In this paper we present a novel technique which can significantly reduce the base-collector capacitance (C/sub bc/) in AlGaAs/GaAs HBTs. C/sub bc/, is a key limiter of HBT microwave gain and bandwidth. Our process uses high dose, high-energy ion implantation through the external base layer to compensate part of the heavily doped sub-collector. It also uses the more conventional self-aligned shallow implant to compensate the entire collector underneath the base contact. The total C/sub bc/ of the double implanted HBTs has been reduced by more than 35% with this new technique as compared to devices with shallow implant only. Under proper conditions, the double implantation produces little damage to the base (which can cause an increase in base resistance R/sub B/); thus the RF performance can be significantly improved. An f/sub MAX/ greater than 200 GHz has been obtained, comparable to the best previous reported results in common emitter HBTs.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131949542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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