Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner

Abstract

Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.