Design Space Exploration for CNN Offloading to FPGAs at the Edge

Guilherme Korol, M. Jordan, M. B. Rutzig, J. Castrillón, A. C. S. Beck
{"title":"Design Space Exploration for CNN Offloading to FPGAs at the Edge","authors":"Guilherme Korol, M. Jordan, M. B. Rutzig, J. Castrillón, A. C. S. Beck","doi":"10.1109/ISVLSI59464.2023.10238644","DOIUrl":null,"url":null,"abstract":"AI-based IoT applications relying on heavy-load deep learning algorithms like CNNs challenge IoT devices that are restricted in energy or processing capabilities. Edge computing offers an alternative by allowing the data to get offloaded to so-called edge servers with hardware more powerful than IoT devices and physically closer than the cloud. However, the increasing complexity of data and algorithms and diverse conditions make even powerful devices, such as those equipped with FPGAs, insufficient to cope with the current demands. In this case, optimizations in the algorithms, like pruning and early-exit, are mandatory to reduce the CNNs computational burden and speed up inference processing. With that in mind, we propose ExpOL, which combines the pruning and early-exit CNN optimizations in a system-level FPGA-based IoT-Edge design space exploration. Based on a user-defined multi-target optimization, ExpOL delivers designs tailored to specific application environments and user needs. When evaluated against state-of-the-art FPGA-based accelerators (either local or offloaded), designs produced by ExpOL are more power-efficient (by up to 2$\\times$) and process inferences at higher user quality of experience (by up to 12.5%).","PeriodicalId":199371,"journal":{"name":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI59464.2023.10238644","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

AI-based IoT applications relying on heavy-load deep learning algorithms like CNNs challenge IoT devices that are restricted in energy or processing capabilities. Edge computing offers an alternative by allowing the data to get offloaded to so-called edge servers with hardware more powerful than IoT devices and physically closer than the cloud. However, the increasing complexity of data and algorithms and diverse conditions make even powerful devices, such as those equipped with FPGAs, insufficient to cope with the current demands. In this case, optimizations in the algorithms, like pruning and early-exit, are mandatory to reduce the CNNs computational burden and speed up inference processing. With that in mind, we propose ExpOL, which combines the pruning and early-exit CNN optimizations in a system-level FPGA-based IoT-Edge design space exploration. Based on a user-defined multi-target optimization, ExpOL delivers designs tailored to specific application environments and user needs. When evaluated against state-of-the-art FPGA-based accelerators (either local or offloaded), designs produced by ExpOL are more power-efficient (by up to 2$\times$) and process inferences at higher user quality of experience (by up to 12.5%).
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
在边缘将CNN分流到fpga的设计空间探索
基于人工智能的物联网应用依赖于cnn等重载深度学习算法,挑战了在能量或处理能力方面受到限制的物联网设备。边缘计算提供了另一种选择,允许数据卸载到所谓的边缘服务器上,这些服务器的硬件比物联网设备更强大,物理上比云更近。然而,随着数据和算法的日益复杂以及条件的多样化,即使是功能强大的设备,如配备fpga的设备,也不足以应对当前的需求。在这种情况下,必须对算法进行优化,如修剪和早期退出,以减少cnn的计算负担并加快推理处理速度。考虑到这一点,我们提出了ExpOL,它在基于系统级fpga的物联网边缘设计空间探索中结合了修剪和早期退出CNN优化。基于用户定义的多目标优化,ExpOL提供针对特定应用环境和用户需求量身定制的设计。当与最先进的基于fpga的加速器(本地或卸载)进行评估时,ExpOL生产的设计更节能(高达2美元),并且在更高的用户体验质量下进行过程推断(高达12.5%)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory 3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems CellFlow: Automated Standard Cell Design Flow Versatile Signal Distribution Networks for Scalable Placement and Routing of Field-coupled Nanocomputing Technologies Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1