A Design of low power Adders

Abstract

The low power adder is designed in this paper using Carry-Select Modified-Tree(CSMT) adder for fast carry generation and for binary addition. The results are analyzed and the performances are compared. This adder makes the use of multiplexers. The greatest advantage of this adder is that it uses very few multiplexers and consumes least amount of energy for specified latency. Carry-select addition is used in the architecture. The adder is implemented using Multiplexer block and longer carry-select adders are be replaced by modified tree structure to maintain the multiplexer complexity. The CSMT architecture in adder can reduce the multiplexer complexity. By using this concept the 3 8 % power is reduced when compared to the conventional adder.