A reduced circuit library design system

Abstract

A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance.<>