A SET Harden Phase-Locked Loop with Perturbation Compensated Charge Pump & Interleaved VCO

Abstract

A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-µm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.