Applications of a mechanistic yield model for MOSIC chips

Abstract

A mechanistic random-defect yield model has been extended to several CMOS technologies and applied to several types of circuit forms. Inputs to the model include critical geometries for yield analysis obtained from detailed layout analysis, and defect density values obtained from large area test structures, with both inputs being needed for each mechanism. A generally applicable yield model metric is proposed to evaluate the effectiveness of any model. Validation of the present model is given in terms of comparisons of model yields (i) with actual yields and (ii) with yield loss per mechanism as determined by physical analysis of non-functional chips. This model is useful in yield improvement work, since it gives a quantitative analysis of yield loss in terms of particular physical mechanisms. The effects of improving an individual processing step can be quantitatively modeled.<>