1.2 micron, high speed, high density CMOS analog library

Abstract

A 1.2- mu m CMOS process was developed for the design of integrated circuits requiring high digital performance combined with high analog performance. In addition, the process allows the integration of 10-V analog circuitry for telecommunication applications. Cells were designed to make use of this technology and incorporated in a test chip. Initial characterization of the ADC (analog-to-digital converter) cell ultrahigh-speed operational amplifiers and latch comparator demonstrated performance commensurate with the needs of high-speed and high-performance analog application.<>