S. Stoukatch, N. André, F. Dupont, Jean-Michel Redouté, D. Flandre
{"title":"Ultra-Thinned Individual SOI Die ACF FC Bonded on Rigid and Flex PCB","authors":"S. Stoukatch, N. André, F. Dupont, Jean-Michel Redouté, D. Flandre","doi":"10.23919/empc53418.2021.9584947","DOIUrl":null,"url":null,"abstract":"We have developed a straightforward die-level thinning process suitable for Silicon-On-Insulator (SOI) dies. The process has been demonstrated on SOI CMOS die assembled on rigid and flexible PCBs using previously-developed anisotropic conductive adhesive flip-chip method. Unlike standard wafer-level thinning processes, in the demonstrated process the full thickness SOI die is directly mounted on PCB and after that thinned. The demonstrated process is simple and robust; it comprises fewer process steps compared to conventional die thinning process. The ultra-thinning process has no effects on the assembly integrity and device performance.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/empc53418.2021.9584947","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We have developed a straightforward die-level thinning process suitable for Silicon-On-Insulator (SOI) dies. The process has been demonstrated on SOI CMOS die assembled on rigid and flexible PCBs using previously-developed anisotropic conductive adhesive flip-chip method. Unlike standard wafer-level thinning processes, in the demonstrated process the full thickness SOI die is directly mounted on PCB and after that thinned. The demonstrated process is simple and robust; it comprises fewer process steps compared to conventional die thinning process. The ultra-thinning process has no effects on the assembly integrity and device performance.