Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584970
S. Stoyanov, P. Stewart, C. Bailey
A micro-Ball Grid Array ($mu$BGAs) is a Chip Scale Package (CSP) architecture that becomes increasingly deployed by electronics manufacturers and used in applications ranging from consumer electronics to high-reliability and high-value equipment operated in harsh environments. In the latter case, design engineers of high-reliability electronics must develop and adopt novel assembly design solutions and new assembly materials that enhance the reliability of such commercial off-the-shelf components. This paper details the results from a comprehensive reliability test program on assessing the thermal fatigue life of $mu$BGA board-level interconnects (quaternary alloy SnPbAgCu solder composition) and from the related physics-of-failure thermo-mechanical modelling. Several package-board assembly designs developed with rigid and compliant printed circuit board (PCB) materials, and with/ without resin application are investigated and discussed. The thermo-mechanical simulation results are used to provide insights into the solder joint physics of failure. The findings confirmed that the reliability of $mu$BGAs can be significantly impacted through assembly design alterations, and lifetime of solder joints can be increased by factor 10X and more. The modelling predictions for solder joint damage and the experimental failure data are used to develop a lifetime model for the thermal fatigue life of $mu$BGA and similar CSP architectures.
{"title":"Reliability Optimisation and Lifetime Modelling of micro-BGA Assemblies in Harsh Environment Applications","authors":"S. Stoyanov, P. Stewart, C. Bailey","doi":"10.23919/empc53418.2021.9584970","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584970","url":null,"abstract":"A micro-Ball Grid Array ($mu$BGAs) is a Chip Scale Package (CSP) architecture that becomes increasingly deployed by electronics manufacturers and used in applications ranging from consumer electronics to high-reliability and high-value equipment operated in harsh environments. In the latter case, design engineers of high-reliability electronics must develop and adopt novel assembly design solutions and new assembly materials that enhance the reliability of such commercial off-the-shelf components. This paper details the results from a comprehensive reliability test program on assessing the thermal fatigue life of $mu$BGA board-level interconnects (quaternary alloy SnPbAgCu solder composition) and from the related physics-of-failure thermo-mechanical modelling. Several package-board assembly designs developed with rigid and compliant printed circuit board (PCB) materials, and with/ without resin application are investigated and discussed. The thermo-mechanical simulation results are used to provide insights into the solder joint physics of failure. The findings confirmed that the reliability of $mu$BGAs can be significantly impacted through assembly design alterations, and lifetime of solder joints can be increased by factor 10X and more. The modelling predictions for solder joint damage and the experimental failure data are used to develop a lifetime model for the thermal fatigue life of $mu$BGA and similar CSP architectures.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117049477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584995
M. D. Sarto, L. Maggi, A. Gritti, A. Maierna, D. Terzi, R. Carminati
MEMS mirrors are among the most promising devices for the new wave of MEMS actuator devices. The general purpose of the devices(s) is to deviate a laser beam and scan a two-dimensional target. To limit the complexity of design and to maximize performances on both axes of scan, two different mirrors are chosen that then need to be coupled mechanically and optically to perform the dual scanning. This paper presents a low cost, high performance, high mass production process capable solution, for a dual mirror single package system.
{"title":"Assembly of MEMS micro mirrors pair system in a single module","authors":"M. D. Sarto, L. Maggi, A. Gritti, A. Maierna, D. Terzi, R. Carminati","doi":"10.23919/empc53418.2021.9584995","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584995","url":null,"abstract":"MEMS mirrors are among the most promising devices for the new wave of MEMS actuator devices. The general purpose of the devices(s) is to deviate a laser beam and scan a two-dimensional target. To limit the complexity of design and to maximize performances on both axes of scan, two different mirrors are chosen that then need to be coupled mechanically and optically to perform the dual scanning. This paper presents a low cost, high performance, high mass production process capable solution, for a dual mirror single package system.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122789135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585007
O. Golim, V. Vuorinen, N. Tiwary, R. Glenn, M. Paulasto-Kröckel
Low-temperature solid-liquid interdiffusion (SLID) bonding is an attractive alternative for the packaging of optical devices. It reduces global residual stress build up caused by differences in coefficient of thermal expansion (CTE) at elevated temperatures. This work applied the Cu-Sn-In-based SLID bonding method to bond silicon and optically transparent materials at 200 °C. Experimental results show a successful bonding with minor unavoidable misalignment from the CTE mismatch and major misalignment from the bonding alignment process. Microstructural analysis shows the intermetallic compound consists only of Cu6(Sn,In)5 on the bond that is thermally stable up to 600 °C.
低温固液互扩散键合是光学器件封装的一种有吸引力的选择。它减少了在高温下由热膨胀系数(CTE)差异引起的全球残余应力积累。这项工作应用了基于cu - sn - in的滑动键合方法，在200°C下键合硅和光透明材料。实验结果表明，成功的键合存在由CTE失配引起的小的不可避免的错位和由键合过程引起的大的错位。显微结构分析表明，该金属间化合物仅由键上的Cu6(Sn,In)5组成，在600℃以下热稳定。
{"title":"Low-temperature Metal Bonding for Optical Device Packaging","authors":"O. Golim, V. Vuorinen, N. Tiwary, R. Glenn, M. Paulasto-Kröckel","doi":"10.23919/empc53418.2021.9585007","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585007","url":null,"abstract":"Low-temperature solid-liquid interdiffusion (SLID) bonding is an attractive alternative for the packaging of optical devices. It reduces global residual stress build up caused by differences in coefficient of thermal expansion (CTE) at elevated temperatures. This work applied the Cu-Sn-In-based SLID bonding method to bond silicon and optically transparent materials at 200 °C. Experimental results show a successful bonding with minor unavoidable misalignment from the CTE mismatch and major misalignment from the bonding alignment process. Microstructural analysis shows the intermetallic compound consists only of Cu6(Sn,In)5 on the bond that is thermally stable up to 600 °C.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128437792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584944
A. Schneider, Dan Beckett, Andrew V. Hill, M. Borri, R. Lemmon, J. Lipp, M. Chartier
Daresbury Laboratory (DL) and Rutherford Appleton Laboratory (RAL) have developed and built radiation detectors for experiments in particle physics since decades. This includes tracker detectors which record the pathway of high energy particles in order to locate the vertexes of decay processes. These tracker detectors need to have low material budget in order to minimize scattering. The most advanced systems comprise thin CMOS sensors (approx. $100 mu mathrm{m}$ thick) which require interconnection to a thin (approx. $150 mu mathrm{m})$ Flexible Printed Circuit (FPC) board which is in turn electrically connected to the data acquisition system. The thickness of detector components and flexibility of the FPC board create challenges for the assembly of these detectors. For detectors described here, an array of 2x2 CMOS sensor chips (each 30mm x 15mm) is mounted onto an FPC creating a module. The chips are positioned in close proximity to each other (approx. $150 mu mathrm{m}$ gap). This paper investigates flip-chip bonding to assemble and interconnect these modules as an alternative to the standard wire bonding technique used in particle physics. For this purpose, two different methods are compared.Method 1: This is considered as the standard method where CMOS sensors are initially bonded to the FPC board with adhesive and subsequently their contact pads are wire bonded to the FPC through large via.Method 2: This is an alternative technique explored in this work where an electrically conductive adhesive is initially printed onto contact pads of the FPC and CMOS sensors are subsequently flip-chip bonded with high precision alignment to the FPC. Prior to this, contact pads on the CMOS sensor are fitted with gold studs.Reported here are considerations on the advantages and disadvantages of the proposed method 2 with respect to the standard method 1. This includes bond yield, mechanical stability of the detector module (adhesion of sensors to FPC), and complexity of the process.
达斯伯里实验室(DL)和卢瑟福阿普尔顿实验室(RAL)几十年来一直在为粒子物理实验开发和建造辐射探测器。这包括跟踪探测器，它记录高能粒子的路径，以便定位衰变过程的顶点。这些跟踪探测器需要有较低的材料预算，以尽量减少散射。最先进的系统包括薄型CMOS传感器(约为10nm)。$100 mu mathm {m}$厚)，这需要连接到一个薄(大约。$150 mu mathm {m})$柔性印刷电路(FPC)板，该板依次电连接到数据采集系统。探测器组件的厚度和FPC板的灵活性为这些探测器的组装带来了挑战。对于这里描述的探测器，2x2 CMOS传感器芯片阵列(每个30mm x 15mm)被安装到创建模块的FPC上。芯片被放置在彼此靠近的位置(大约。$150 mu mathm {m}$ gap)。本文研究了倒装芯片键合来组装和互连这些模块，作为粒子物理中使用的标准线键合技术的替代方案。为此，比较了两种不同的方法。方法1:这被认为是标准方法，其中CMOS传感器最初用粘合剂粘合到FPC板上，随后它们的接触垫通过大通孔与FPC连接。方法2:这是本研究中探索的一种替代技术，首先将导电粘合剂印刷在FPC的接触片上，然后将CMOS传感器与FPC进行高精度对准的倒装芯片粘合。在此之前，CMOS传感器上的触点垫配有金螺柱。这里报告的是关于相对于标准方法1的建议方法2的优点和缺点的考虑。这包括债券收益率，探测器模块的机械稳定性(传感器与FPC的粘附性)，以及过程的复杂性。
{"title":"Thin Si Sensors on Flexible Printed Circuits – Study of Two Bond Methods","authors":"A. Schneider, Dan Beckett, Andrew V. Hill, M. Borri, R. Lemmon, J. Lipp, M. Chartier","doi":"10.23919/empc53418.2021.9584944","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584944","url":null,"abstract":"Daresbury Laboratory (DL) and Rutherford Appleton Laboratory (RAL) have developed and built radiation detectors for experiments in particle physics since decades. This includes tracker detectors which record the pathway of high energy particles in order to locate the vertexes of decay processes. These tracker detectors need to have low material budget in order to minimize scattering. The most advanced systems comprise thin CMOS sensors (approx. $100 mu mathrm{m}$ thick) which require interconnection to a thin (approx. $150 mu mathrm{m})$ Flexible Printed Circuit (FPC) board which is in turn electrically connected to the data acquisition system. The thickness of detector components and flexibility of the FPC board create challenges for the assembly of these detectors. For detectors described here, an array of 2x2 CMOS sensor chips (each 30mm x 15mm) is mounted onto an FPC creating a module. The chips are positioned in close proximity to each other (approx. $150 mu mathrm{m}$ gap). This paper investigates flip-chip bonding to assemble and interconnect these modules as an alternative to the standard wire bonding technique used in particle physics. For this purpose, two different methods are compared.Method 1: This is considered as the standard method where CMOS sensors are initially bonded to the FPC board with adhesive and subsequently their contact pads are wire bonded to the FPC through large via.Method 2: This is an alternative technique explored in this work where an electrically conductive adhesive is initially printed onto contact pads of the FPC and CMOS sensors are subsequently flip-chip bonded with high precision alignment to the FPC. Prior to this, contact pads on the CMOS sensor are fitted with gold studs.Reported here are considerations on the advantages and disadvantages of the proposed method 2 with respect to the standard method 1. This includes bond yield, mechanical stability of the detector module (adhesion of sensors to FPC), and complexity of the process.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584954
Markus Enmark, Yifeng Fu, T. Nilsson, Johan Liu
The increasing need for high thermal dissipation in small electronic products puts tough requirements on effective cooling solutions. Two of the most effective passive cooling devices in electronics today are vapor chambers and heat pipes. With new advancements in materials science and nanotechnology comes the possibility to further increase cooling capacity and at the same time make devices lighter. This study is a critical assessment on recent progress in the field of nanomaterial enhanced wick structures in vapor chambers and heat pipes. In this paper, nano-enhanced wick structures are divided into five different sub-categories based on material type. Publication trends for the different types of nano-enhanced wicks are studied by plotting them on a timeline. It is found that nanostructured metal wicks is the most studied field in recent years. A plot showing wick performance in terms of superheat temperatures for given heat flux is created to be used for benchmarking of new wick structures when pool boil experiments are carried out. An attempt to find correlation between publication trends, type of wick and performance is done. On the basis of the gathered data it is deemed difficult to find a distinct correlation, this is mainly due to difficulty in comparing performance between different studies, especially when different heat fluxes are used. There is no unambiguous answer to which category of nano-enhanced wicks that should be target for future studies. Graphene coating and pure carbon nanomaterials such as aerogels and graphene foam are still relatively unexplored and believed to have great potential if they can be attached to envelope materials.
{"title":"A Critical Assessment of Nano Enhanced Vapor Chamber Wick Structures for Electronics Cooling","authors":"Markus Enmark, Yifeng Fu, T. Nilsson, Johan Liu","doi":"10.23919/empc53418.2021.9584954","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584954","url":null,"abstract":"The increasing need for high thermal dissipation in small electronic products puts tough requirements on effective cooling solutions. Two of the most effective passive cooling devices in electronics today are vapor chambers and heat pipes. With new advancements in materials science and nanotechnology comes the possibility to further increase cooling capacity and at the same time make devices lighter. This study is a critical assessment on recent progress in the field of nanomaterial enhanced wick structures in vapor chambers and heat pipes. In this paper, nano-enhanced wick structures are divided into five different sub-categories based on material type. Publication trends for the different types of nano-enhanced wicks are studied by plotting them on a timeline. It is found that nanostructured metal wicks is the most studied field in recent years. A plot showing wick performance in terms of superheat temperatures for given heat flux is created to be used for benchmarking of new wick structures when pool boil experiments are carried out. An attempt to find correlation between publication trends, type of wick and performance is done. On the basis of the gathered data it is deemed difficult to find a distinct correlation, this is mainly due to difficulty in comparing performance between different studies, especially when different heat fluxes are used. There is no unambiguous answer to which category of nano-enhanced wicks that should be target for future studies. Graphene coating and pure carbon nanomaterials such as aerogels and graphene foam are still relatively unexplored and believed to have great potential if they can be attached to envelope materials.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132645958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584975
D. Manessis, Stefan Kosmider, L. Boettcher, M. Seckel, K. Murugesan, U. Maass, I. Ndip, A. Ostmann, R. Aschenbrenner, M. Schneider-Ramelow, K. Lang
This paper brings into light all the new developmental work performed in the wide domain of high frequency PCBs for the realisation of innovative metasurfaces at 5GHz as well as compact highly integrated 5G antenna-in-modules at 40 GHz. There is a fast growing demand in high frequency market that justifies the intense R&D work also on microwave and especially mmWave technologies, comprising both “beyond the state-of-the-art high frequency PCBs” and advanced PCB integration concepts. In this context, this paper intends to highlight new knowledge in materials, processes as well as thermal dissipation concepts, that have been derived from various R&D projects, but especially in the framework of the FET-EU “Visorsurf” and the EU-Serena projects. In specific, R&D work will be shown on the emerging concepts of metamaterials that can be software programmable and adapt their properties. The Visorsurf main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be programmatically defined. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials with the metasurfaces on the top and custom electronic controller nodes at the bottom of the PCB hardware platform. This paper will elaborate on how innovative PCB processes have been tailored to high frequency substrates for the manufacturing of the first 4-layer Hypersurface PCB hardware platform with a size of 300mmx300mm.}{In a complimentary way, the paper will describe in detail new chip embedding concepts in the same family of high frequency PCB substrates toward the realization of highly miniaturized advanced packages for 5G mmWave applications at 40 GHz. These concepts show vividly the potential of PCB embedding technologies as the mean for heterogeneous integration in high frequency advanced packages/modules. The paper discusses in detail all process chain developments in high frequency PCBs for the embedding of GaN and SiGe chips in PCBs, their interconnection path concept, the embedding of passives, the fabrication of the antenna module and its stacking on a high power or low power PCB module for the final formation of a 6-layer antenna-in-module package which could be separately assembled on the system board. Furthermore, the paper will present for the first time innovative thermal dissipation concepts for the “Serena” antenna module, with the prevailing scenario of thermal vias to the bottom of the GaN and SiGe chips for direct heat removal. All processes for realization of high frequency substrates and embedded 5G 40 GHz antenna modules will be discussed in detail.
{"title":"Development of innovative substrate and embedding technologies for high frequency applications","authors":"D. Manessis, Stefan Kosmider, L. Boettcher, M. Seckel, K. Murugesan, U. Maass, I. Ndip, A. Ostmann, R. Aschenbrenner, M. Schneider-Ramelow, K. Lang","doi":"10.23919/empc53418.2021.9584975","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584975","url":null,"abstract":"This paper brings into light all the new developmental work performed in the wide domain of high frequency PCBs for the realisation of innovative metasurfaces at 5GHz as well as compact highly integrated 5G antenna-in-modules at 40 GHz. There is a fast growing demand in high frequency market that justifies the intense R&D work also on microwave and especially mmWave technologies, comprising both “beyond the state-of-the-art high frequency PCBs” and advanced PCB integration concepts. In this context, this paper intends to highlight new knowledge in materials, processes as well as thermal dissipation concepts, that have been derived from various R&D projects, but especially in the framework of the FET-EU “Visorsurf” and the EU-Serena projects. In specific, R&D work will be shown on the emerging concepts of metamaterials that can be software programmable and adapt their properties. The Visorsurf main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be programmatically defined. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials with the metasurfaces on the top and custom electronic controller nodes at the bottom of the PCB hardware platform. This paper will elaborate on how innovative PCB processes have been tailored to high frequency substrates for the manufacturing of the first 4-layer Hypersurface PCB hardware platform with a size of 300mmx300mm.}{In a complimentary way, the paper will describe in detail new chip embedding concepts in the same family of high frequency PCB substrates toward the realization of highly miniaturized advanced packages for 5G mmWave applications at 40 GHz. These concepts show vividly the potential of PCB embedding technologies as the mean for heterogeneous integration in high frequency advanced packages/modules. The paper discusses in detail all process chain developments in high frequency PCBs for the embedding of GaN and SiGe chips in PCBs, their interconnection path concept, the embedding of passives, the fabrication of the antenna module and its stacking on a high power or low power PCB module for the final formation of a 6-layer antenna-in-module package which could be separately assembled on the system board. Furthermore, the paper will present for the first time innovative thermal dissipation concepts for the “Serena” antenna module, with the prevailing scenario of thermal vias to the bottom of the GaN and SiGe chips for direct heat removal. All processes for realization of high frequency substrates and embedded 5G 40 GHz antenna modules will be discussed in detail.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132023004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584997
Pascal Sobek, K. Reinhardt, S. Körner
Fraunhofer IKTS presents first results of thick-film Constantan pastes as an attractive alternative for resistor and heater applications. We report on influencing the sheet resistance of screen-printed Constantan pastes by variation of paste composition and constitution, as well as architectural conditions. It is shown, how to adjust sheet resistance of Constantan pastes over a range of multiple orders of magnitude. Investigations of the structure of the fired pastes reveal a change of composition of the annealed pastes. Experiments using a new adapted glass promise suppression of those changes.
{"title":"Reasonable resistor pastes with low TCR using Constantan","authors":"Pascal Sobek, K. Reinhardt, S. Körner","doi":"10.23919/empc53418.2021.9584997","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584997","url":null,"abstract":"Fraunhofer IKTS presents first results of thick-film Constantan pastes as an attractive alternative for resistor and heater applications. We report on influencing the sheet resistance of screen-printed Constantan pastes by variation of paste composition and constitution, as well as architectural conditions. It is shown, how to adjust sheet resistance of Constantan pastes over a range of multiple orders of magnitude. Investigations of the structure of the fired pastes reveal a change of composition of the annealed pastes. Experiments using a new adapted glass promise suppression of those changes.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125513277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9585012
K. Vogel, Ralph Schachler, F. Roscher, M. Wiemer, H. Kuhn
Reactive bonding is a new innovative technology for room temperature bonding of wafers chips and components within seconds. The CuO/Al reactive multilayer system shows great potential as internal heat source for wafer and chip level packaging of optical microsystems. The transfer of the material from wafer to chip level enables a fast integration without additional heating and cooling steps. The ignition of the reaction can be achieved by direct spark or laser ignition as well as indirect potential based ignition. The demand for particle free bonding in optical systems also favors the indirect ignition. Furthermore, the shear strength of the chip bonded Si-glass samples strongly depends on a successful wedge compensation, enabling an increase of the average shear strength by 37 %.
{"title":"Reactive chip level bonding based on CuO/Al reactive multilayer systems","authors":"K. Vogel, Ralph Schachler, F. Roscher, M. Wiemer, H. Kuhn","doi":"10.23919/empc53418.2021.9585012","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9585012","url":null,"abstract":"Reactive bonding is a new innovative technology for room temperature bonding of wafers chips and components within seconds. The CuO/Al reactive multilayer system shows great potential as internal heat source for wafer and chip level packaging of optical microsystems. The transfer of the material from wafer to chip level enables a fast integration without additional heating and cooling steps. The ignition of the reaction can be achieved by direct spark or laser ignition as well as indirect potential based ignition. The demand for particle free bonding in optical systems also favors the indirect ignition. Furthermore, the shear strength of the chip bonded Si-glass samples strongly depends on a successful wedge compensation, enabling an increase of the average shear strength by 37 %.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584990
P. Papatzacos, N. Tiwary, N. Hoivik, Hoang-Vu Nguyen, A. Roy, K. Aasmundtveit
Cu-Sn SLID is an increasingly popular bonding technique with applications in such as hermetic sealing of microbolometers. A moderate bonding pressure is necessary to compensate for the surface roughness of the electroplated layers and to break the Sn oxide layer, thereby reducing the risk of voiding. However, such bonding pressures increase the risk for Sn squeeze-out during the bonding process, which has the potential to destroy MEMS or ROIC devices. To prevent this potential issue, an alternative bondline geometry consisting of 3x50µm wide bond rails and 25µm wide gaps was manufactured and compared to a continuous 200µm bondline by using nondestructive IR imaging, cross-sectional microscopy, and die-shear testing. High shear strength values of 31±9MPa and 43±18MPa were obtained for continuous and railed seal frames respectively. The Sn squeeze-out distance beyond the intended bondline was, on average, reduced by 60% when the railed geometry is employed. A reduction in peak squeeze-out distance from 188µm to 54µm was also observed.
{"title":"Investigation of seal frame geometry on Sn squeeze-out in Cu-Sn SLID bonds","authors":"P. Papatzacos, N. Tiwary, N. Hoivik, Hoang-Vu Nguyen, A. Roy, K. Aasmundtveit","doi":"10.23919/empc53418.2021.9584990","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584990","url":null,"abstract":"Cu-Sn SLID is an increasingly popular bonding technique with applications in such as hermetic sealing of microbolometers. A moderate bonding pressure is necessary to compensate for the surface roughness of the electroplated layers and to break the Sn oxide layer, thereby reducing the risk of voiding. However, such bonding pressures increase the risk for Sn squeeze-out during the bonding process, which has the potential to destroy MEMS or ROIC devices. To prevent this potential issue, an alternative bondline geometry consisting of 3x50µm wide bond rails and 25µm wide gaps was manufactured and compared to a continuous 200µm bondline by using nondestructive IR imaging, cross-sectional microscopy, and die-shear testing. High shear strength values of 31±9MPa and 43±18MPa were obtained for continuous and railed seal frames respectively. The Sn squeeze-out distance beyond the intended bondline was, on average, reduced by 60% when the railed geometry is employed. A reduction in peak squeeze-out distance from 188µm to 54µm was also observed.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126904393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-13DOI: 10.23919/empc53418.2021.9584998
C. Tschoban, S. Dilek, I. Ndip, H. Pötter, K. Lang, M. Schneider-Ramelow
Non-touch interface technology will be used more and more in future electronic systems. This paper describes the development of a novel sensor element for such interfaces. In this work, we apply a systematic approach, the M3-approach (methodologies, models, measures), to design miniaturized, scalable and low-cost 60 GHz MIMO (Multiple Input Multiple Output) radar front-ends for the integration of a novel non-touch human interface into a table. The packaging technology applied for the development of this radar module is suitable for mass production. The complete application of the M3-approach requires the implementation of three key steps, namely methodologies, models and measures. However, in this paper, we focus on the first two steps (i.e., methodologies and models) and describe these steps in detail.
{"title":"Development of a 60GHz MIMO Radar Packaging Concept","authors":"C. Tschoban, S. Dilek, I. Ndip, H. Pötter, K. Lang, M. Schneider-Ramelow","doi":"10.23919/empc53418.2021.9584998","DOIUrl":"https://doi.org/10.23919/empc53418.2021.9584998","url":null,"abstract":"Non-touch interface technology will be used more and more in future electronic systems. This paper describes the development of a novel sensor element for such interfaces. In this work, we apply a systematic approach, the M3-approach (methodologies, models, measures), to design miniaturized, scalable and low-cost 60 GHz MIMO (Multiple Input Multiple Output) radar front-ends for the integration of a novel non-touch human interface into a table. The packaging technology applied for the development of this radar module is suitable for mass production. The complete application of the M3-approach requires the implementation of three key steps, namely methodologies, models and measures. However, in this paper, we focus on the first two steps (i.e., methodologies and models) and describe these steps in detail.","PeriodicalId":348887,"journal":{"name":"2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC)","volume":"156 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131590232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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