Controlled Formation of Square Crack in Thinned 3DI Silicon Wafers

Abstract

The advancement of package technology to enable die to die interconnects have allowed Integrated Circuit (IC) technology to progress into much higher density region. The fabrication process requires wafers to be processed at lower thicknesses while bonded to a carrier. The forces applied to the thin wafer often generate localized stress fields that cause Si defects to propagate in a form of cracks. This paper demonstrates a new type of crack that is observed during processing of the wafers. The crack usually takes place in the center of the wafer, oriented with the crystalline plane and is approximately 100mm square with rounded corners. This paper also discusses a methodology to replicate the defect in bare test wafers as the first step in understanding the conditions required to create such a defect.