Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093689
A. Abdelnaby, R. Parker, Pavani Chennapragada, S. Vadhavkar, Wayne Huang, M. Brand, S. Varghese, Ross Dando
The advancement of package technology to enable die to die interconnects have allowed Integrated Circuit (IC) technology to progress into much higher density region. The fabrication process requires wafers to be processed at lower thicknesses while bonded to a carrier. The forces applied to the thin wafer often generate localized stress fields that cause Si defects to propagate in a form of cracks. This paper demonstrates a new type of crack that is observed during processing of the wafers. The crack usually takes place in the center of the wafer, oriented with the crystalline plane and is approximately 100mm square with rounded corners. This paper also discusses a methodology to replicate the defect in bare test wafers as the first step in understanding the conditions required to create such a defect.
{"title":"Controlled Formation of Square Crack in Thinned 3DI Silicon Wafers","authors":"A. Abdelnaby, R. Parker, Pavani Chennapragada, S. Vadhavkar, Wayne Huang, M. Brand, S. Varghese, Ross Dando","doi":"10.1109/WMED.2015.7093689","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093689","url":null,"abstract":"The advancement of package technology to enable die to die interconnects have allowed Integrated Circuit (IC) technology to progress into much higher density region. The fabrication process requires wafers to be processed at lower thicknesses while bonded to a carrier. The forces applied to the thin wafer often generate localized stress fields that cause Si defects to propagate in a form of cracks. This paper demonstrates a new type of crack that is observed during processing of the wafers. The crack usually takes place in the center of the wafer, oriented with the crystalline plane and is approximately 100mm square with rounded corners. This paper also discusses a methodology to replicate the defect in bare test wafers as the first step in understanding the conditions required to create such a defect.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128195875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093954
Bingxing Wu, S. Ay
This paper presents a low-noise CMOS bandgap reference (BGR) circuit that uses two-level chopping technique to reduce errors caused by non-idealities of the OPAMP used in the design. Input referred offset voltage of the OPAMP is reduced on first level. On second level, OPAMP offset is further reduced along with the low-frequency 1/f noise caused by the input transistors of the two-stage Miller OPAMP. The design is fabricated in a 0.35μm 2P4M CMOS analog process. The proposed BGR was tested in a temperature chamber between -25oC and +125oC. Measurement results showed that the standard deviation of the BGR output voltage without chopping is 7 times higher than that of when chopping is enabled. The proposed two-level chopping technique is verified improving performance characteristics of conventional BGR circuit.
{"title":"Low-Noise CMOS Bandgap Reference Generator Using Two-Level Chopping Technique","authors":"Bingxing Wu, S. Ay","doi":"10.1109/WMED.2015.7093954","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093954","url":null,"abstract":"This paper presents a low-noise CMOS bandgap reference (BGR) circuit that uses two-level chopping technique to reduce errors caused by non-idealities of the OPAMP used in the design. Input referred offset voltage of the OPAMP is reduced on first level. On second level, OPAMP offset is further reduced along with the low-frequency 1/f noise caused by the input transistors of the two-stage Miller OPAMP. The design is fabricated in a 0.35μm 2P4M CMOS analog process. The proposed BGR was tested in a temperature chamber between -25oC and +125oC. Measurement results showed that the standard deviation of the BGR output voltage without chopping is 7 times higher than that of when chopping is enabled. The proposed two-level chopping technique is verified improving performance characteristics of conventional BGR circuit.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129376861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093691
S. Aghaei, P. Andrei, M. Hagmann
In this article we investigate the possibility to use scanning capacitance microscopy (SCM) for 3-D dopant profiling. It is shown that SCM with probes that have a radius under 10 nm, could be potentially used to determine the x-y-z coordinates of the doping atoms (or ionized impurities) in a layer of a thickness equal to the width of the depletion region. An inversion algorithm that computes the locations of the dopants from the experimental capacitance-voltage (C-V) measurements is presented for the first time. The algorithm is based on the evaluation of the doping sensitivity functions of the differential capacitance and uses a gradient-based iterative method to compute the locations of the dopants.
{"title":"\"Atomistic\" Dopant Profiling Using Scanning Capacitance Microscopy","authors":"S. Aghaei, P. Andrei, M. Hagmann","doi":"10.1109/WMED.2015.7093691","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093691","url":null,"abstract":"In this article we investigate the possibility to use scanning capacitance microscopy (SCM) for 3-D dopant profiling. It is shown that SCM with probes that have a radius under 10 nm, could be potentially used to determine the x-y-z coordinates of the doping atoms (or ionized impurities) in a layer of a thickness equal to the width of the depletion region. An inversion algorithm that computes the locations of the dopants from the experimental capacitance-voltage (C-V) measurements is presented for the first time. The algorithm is based on the evaluation of the doping sensitivity functions of the differential capacitance and uses a gradient-based iterative method to compute the locations of the dopants.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093690
Kehan Zhu, V. Saxena, Xinyu Wu, S. Balagopal
A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz reference clock with 4.9 ps rms jitter from a 0.05 to 12.5 GHz signal generator. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.
{"title":"Design Analysis of a 12.5 GHz PLL in 130 Nm SiGe BiCMOS Process","authors":"Kehan Zhu, V. Saxena, Xinyu Wu, S. Balagopal","doi":"10.1109/WMED.2015.7093690","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093690","url":null,"abstract":"A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz reference clock with 4.9 ps rms jitter from a 0.05 to 12.5 GHz signal generator. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093692
D. Elgamel, Roy Greeff, David Ovard
Approximation of the Rational Function (RF) order plays a key role in passivity checking of large interconnect memory design. RF approximation can be estimated using the Least- square solutions; the Singular Value Decomposition (SVD) is used to solve large order macromodels. The interpolation method is used to solve linear systems by approximating the RF degree and coefficients. However, building the macromodel requires RF order approximation, which can lead to inaccurate passivity checking for complex systems. While inaccurate order estimation may lead to inaccuracy in the passivity checking process and drive to unnecessary passivity enforcement to the macromodel. Inaccurate passivity enforcement perturbation may cause large error adds up to the RF approximation, and may change the original design characteristics. Thus, passivity verification for larger order models requires determining the RF order, using the SVD resolved the inaccurate prior estimation of the model order, yet it yields to an exact solution. SVD is considered an expensive computational algorithm, but SVD shows accurate models order approximation. Using the SVD solved the problem associated with the passivity checking algorithm, which is estimating the initial number of poles or the model order. However, the correlation between determining the model order degree and passivity checking did not exist before. The DC frequency band and the truncation frequency point may lead to some residuals that affect the accuracy of this estimation. Using SVD to solve linear systems enhances the passivity checking of DRAM memory package and high end computers reduces the computation time.
{"title":"Passivity Verification and Macromodel Interpolation Using Singular Value Decomposition (SVD)","authors":"D. Elgamel, Roy Greeff, David Ovard","doi":"10.1109/WMED.2015.7093692","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093692","url":null,"abstract":"Approximation of the Rational Function (RF) order plays a key role in passivity checking of large interconnect memory design. RF approximation can be estimated using the Least- square solutions; the Singular Value Decomposition (SVD) is used to solve large order macromodels. The interpolation method is used to solve linear systems by approximating the RF degree and coefficients. However, building the macromodel requires RF order approximation, which can lead to inaccurate passivity checking for complex systems. While inaccurate order estimation may lead to inaccuracy in the passivity checking process and drive to unnecessary passivity enforcement to the macromodel. Inaccurate passivity enforcement perturbation may cause large error adds up to the RF approximation, and may change the original design characteristics. Thus, passivity verification for larger order models requires determining the RF order, using the SVD resolved the inaccurate prior estimation of the model order, yet it yields to an exact solution. SVD is considered an expensive computational algorithm, but SVD shows accurate models order approximation. Using the SVD solved the problem associated with the passivity checking algorithm, which is estimating the initial number of poles or the model order. However, the correlation between determining the model order degree and passivity checking did not exist before. The DC frequency band and the truncation frequency point may lead to some residuals that affect the accuracy of this estimation. Using SVD to solve linear systems enhances the passivity checking of DRAM memory package and high end computers reduces the computation time.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093687
Lifang Xu, Alan Shafi, Mark Meldrim, Zengtao Liu, Yudong Kim, N. Rangaraju
The effect of multiple Si processes on the intrinsic sheet resistance of CoSi2 resistors is investigated in this article. It is discovered that CoSi2 intrinsic sheet resistance is not a simple function of the CoSi thickness, but rather depends on many other factors including CD related poly grain size, the mushroom effect, diffusion of As implant during silicidation anneal, and the existence of Ti-Under layer. The findings of this study provided an accurate and stable resistance control on Silicided poly resistor applications.
{"title":"Salicidation Processes and CoSi2 Resistance Study","authors":"Lifang Xu, Alan Shafi, Mark Meldrim, Zengtao Liu, Yudong Kim, N. Rangaraju","doi":"10.1109/WMED.2015.7093687","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093687","url":null,"abstract":"The effect of multiple Si processes on the intrinsic sheet resistance of CoSi2 resistors is investigated in this article. It is discovered that CoSi2 intrinsic sheet resistance is not a simple function of the CoSi thickness, but rather depends on many other factors including CD related poly grain size, the mushroom effect, diffusion of As implant during silicidation anneal, and the existence of Ti-Under layer. The findings of this study provided an accurate and stable resistance control on Silicided poly resistor applications.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131816974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093688
S. Qin
Channeling effect factor (CEF), self-sputtering effect, and amorphous (a-Si) layer thickness data as a function of ion mass (AMU) were measured and quantified by SIMS measurements, SRIM simulations, and HR-TEM measurements. Least squares fitting algorithm is used to fit measurement data. Good agreements between the modeling fitting curve and the measurement data are demonstrated. CEF is a logarithm function of the ion AMU. Self-sputtering is independent on the ion AMU for constant implant energy and dose. Amorphous (a-Si) layer thickness is a linear function of the ion AMU.
{"title":"Study of Channeling and Self-Sputtering Effects of Ion Implantation - Data and Modeling","authors":"S. Qin","doi":"10.1109/WMED.2015.7093688","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093688","url":null,"abstract":"Channeling effect factor (CEF), self-sputtering effect, and amorphous (a-Si) layer thickness data as a function of ion mass (AMU) were measured and quantified by SIMS measurements, SRIM simulations, and HR-TEM measurements. Least squares fitting algorithm is used to fit measurement data. Good agreements between the modeling fitting curve and the measurement data are demonstrated. CEF is a logarithm function of the ion AMU. Self-sputtering is independent on the ion AMU for constant implant energy and dose. Amorphous (a-Si) layer thickness is a linear function of the ion AMU.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121726778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-20DOI: 10.1109/WMED.2015.7093953
H. Tran, L. Barannyk, A. Elshabini, F. Barlow
Low voltage differential signaling (LVDS) in high-speed digital systems is utilized to effectively reduce EMI and improve signal quality. Mixed-mode S-parameters are a more general way to characterize a differential network. Therefore, an accurate extraction of mixed-mode S-parameters from single-ended S- parameters is critical for Signal and Power Integrity co-simulation where SSN is generated mainly by high-frequency interconnects. The standard conversion between mixed-mode and single-ended S-parameters involves inversion of a transformation matrix. If there is no coupling, this transformation matrix is orthogonal and numerical inversion can be done accurately. In the presence of coupling, the transformation matrix depends on S-parameters and may become ill-conditioned, i.e. has high condition number, for some values of physical parameters resulting in unstable inversion of the transformation matrix and leading to highly inaccurate converted mixed-mode S-parameters. To analyze the possibility of ill-conditioning, we consider two cases: broadside coupled striplines and coupled microstrip pairs. We find that in both cases when two transmission lines are strongly coupled, the condition number becomes very large. In this case, regularized methods from the theory of ill-posed problems should be used, for example, the truncated SVD method, to obtain accurate mixed-mode S- parameters.
{"title":"A Study of Differential Signaling: Stable and Accurate Mixed-Mode Conversion and Extraction of Differential S-Parameters","authors":"H. Tran, L. Barannyk, A. Elshabini, F. Barlow","doi":"10.1109/WMED.2015.7093953","DOIUrl":"https://doi.org/10.1109/WMED.2015.7093953","url":null,"abstract":"Low voltage differential signaling (LVDS) in high-speed digital systems is utilized to effectively reduce EMI and improve signal quality. Mixed-mode S-parameters are a more general way to characterize a differential network. Therefore, an accurate extraction of mixed-mode S-parameters from single-ended S- parameters is critical for Signal and Power Integrity co-simulation where SSN is generated mainly by high-frequency interconnects. The standard conversion between mixed-mode and single-ended S-parameters involves inversion of a transformation matrix. If there is no coupling, this transformation matrix is orthogonal and numerical inversion can be done accurately. In the presence of coupling, the transformation matrix depends on S-parameters and may become ill-conditioned, i.e. has high condition number, for some values of physical parameters resulting in unstable inversion of the transformation matrix and leading to highly inaccurate converted mixed-mode S-parameters. To analyze the possibility of ill-conditioning, we consider two cases: broadside coupled striplines and coupled microstrip pairs. We find that in both cases when two transmission lines are strongly coupled, the condition number becomes very large. In this case, regularized methods from the theory of ill-posed problems should be used, for example, the truncated SVD method, to obtain accurate mixed-mode S- parameters.","PeriodicalId":251088,"journal":{"name":"2015 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"394 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133938708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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