FAULT MODELING FOR THE TESTING OF MIXED INTEGRATED CIRCUITS

A. Meixner, Wojciech Maly
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引用次数: 92

Abstract

The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.
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混合集成电路测试的故障建模
本文的研究目标是介绍一种故障建模技术,用于模拟混合模拟/数字集成电路中有缺陷的模拟元件。所提出的故障建模策略已被实施,以建立模拟故障模型来表示CMOS电路中点缺陷的影响。总结了opamp的初步研究结果,并包括一个实例的详细结果,以说明故障建模过程。模拟元件在大型数字系统中的应用-现代混合模拟/数字集成电路的典型配置-在设计和测试领域(1),(2),(3),(4)中产生了许多新的挑战。由于混合集成电路的数字和模拟元件之间的边界性质造成的可观察性限制,测试问题尤其难以解决。虽然混合集成电路的测试问题很多,但本文只关注其中的一个问题——故障模拟策略。更具体地说,本文介绍了一种故障建模方法,该方法可用于捕获混合集成电路中模拟元件的故障。报告研究的目标是开发故障模型,通过使用尽可能接近传统数字电路仿真技术的技术,实现对整个混合IC的有效仿真。因此,本文主要研究故障建模技术。它的组织方式如下。在第2节中,介绍了为混合集成电路的模拟组件开发的一般故障建模方法。在第3节中,对CMOS技术的这种方法的实现进行了更详细的描述。最后,在第4节中,为了确定所提出的故障建模方法的实用性,对所获得的结果进行了推广。本节还列出了在后续研究中处理混合模拟/数字集成电路测试需要解决的问题。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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