T. Song, S. M. Lee, Jaehyouk Choi, Stephen T. Kim, Gyuhong Kim, K. Lim, J. Laskar
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引用次数: 3
Abstract
A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.
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