Modeling and scaling evaluation of junction-free charge-trapping NAND flash devices

Abstract

The “junction-free” charge-trapping NAND Flash [1,2] is studied extensively. Simulation results show that the junction-free NAND Flash is scalable beyond 15 nm node (half pitch) with reasonable DC characteristics, while the conventional “with-junction” NAND device shows much worse short-channel effect. Simulation results show that lower p-well doping and smaller space (S) between the WL's are two key factors to enable the higher performance of junction-free NAND device. For the first time, we point out that the parameters of the region under the space (S) such as interface traps (Dit), parasitic trapped charge, and local p-well doping have strong impact on cell characteristics. Experimental results on junction-free BE-SONOS device showed some discrepancy with the simulation that may be due to non-ideal factors under the space. Finally, the feasibility of junction-free device on SOI for the future 3D NAND Flash is also examined.