Application of scanning capacitance microscopy on SOI wafer in die-level failure analysis

Abstract

With the presence of Buried Oxide (BOX) layer in Silicon On Insulator (SOI) wafer, local defect isolation by using Conductive Atomic Force Microscopy (C-AFM) in die-level failure analysis is not feasible as electric current is unable to pass through the BOX layer. To overcome this limitation, Scanning Capacitance Microscopy (SCM) is used to perform local defect isolation in die-level failure analysis. Investigation was performed to evaluate the type of SCM probes which gave high signal sensitivity. Case study on sample with leakage through the SOI substrate is demonstrated and presented in this paper.