Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design

Abstract

Graphene barristor, in which a Schottky barrier formed between graphene layer and silicon layer can widen the bandgap with the control of gate voltage, is a promising method to enhance on/off current ratio in digital circuit design. In this work, a theoretical study is presented based on analog behavior modeling in SPICE. We have developed a compact device model to evaluate the performance of graphene barristors. The device simulation results show the on/off current ratio nearly 105 under the voltage variation which agrees closely with the reported experimental results. A complementary inverter is designed using the developed model to prove the feasibility of graphene barristor for use in future digital VLSI design. The energy per switching is between 1.1±0.52fJ under voltage variation.