{"title":"A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output","authors":"E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti","doi":"10.1109/ICICDT.2010.5510246","DOIUrl":null,"url":null,"abstract":"A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"156 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.