A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output

E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti
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引用次数: 6

Abstract

A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.
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6mW, 115GHz CMOS注入锁定倍频器,差分输出
报道了一种毫米波CMOS倍频器。该电路由一个皮尔斯振荡器组成,该振荡器由推-推对注入锁定。传统的乘频器利用有源器件的非线性产生输入信号的谐波,与之相比,该技术提供了信号平衡、低芯功耗和大摆幅的差分输出。通过建立电路模型,推导出频率锁定范围的封闭形式表达式。该倍频器的原型已经在65nm CMOS技术上实现,工作带宽从106GHz到128GHz,核心功耗为6mW。在输入功率为0dBm时,输出峰值电压摆幅,为330mV,频率为115GHz。
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