{"title":"Combined Vramp and TDDB analysis for gate oxide reliability assessment and screening","authors":"T. Kopley, M. Ring, C. Choi, J. Colbath","doi":"10.1109/IIRW.2015.7437087","DOIUrl":null,"url":null,"abstract":"We present a gate oxide breakdown analysis method that uses an effective oxide thickness model combined with Time-Dependent Dielectric Breakdown (TDDB) model parameters to assess the reliability of extrinsic gate oxide defects. The method transforms gate breakdown voltage (Vbd), obtained from voltage ramp-to-breakdown measurements, into effective oxide thickness (teff) and compares these to the minimum oxide thickness that gives 10 or 20 years TDDB lifetimes. The analysis allows binning of extrinsic defects (Jedec mode B) into reliable and unreliable populations. It also gives an optimal gate screen voltage that can be used at wafer sort to screen parts with unreliable gate oxides. This method is valid for any CMOS process, but is especially useful for BCDMOS and Power Trench MOSFET technologies that use very large devices and ship in large volumes.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2015.7437087","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
We present a gate oxide breakdown analysis method that uses an effective oxide thickness model combined with Time-Dependent Dielectric Breakdown (TDDB) model parameters to assess the reliability of extrinsic gate oxide defects. The method transforms gate breakdown voltage (Vbd), obtained from voltage ramp-to-breakdown measurements, into effective oxide thickness (teff) and compares these to the minimum oxide thickness that gives 10 or 20 years TDDB lifetimes. The analysis allows binning of extrinsic defects (Jedec mode B) into reliable and unreliable populations. It also gives an optimal gate screen voltage that can be used at wafer sort to screen parts with unreliable gate oxides. This method is valid for any CMOS process, but is especially useful for BCDMOS and Power Trench MOSFET technologies that use very large devices and ship in large volumes.