Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437086
G. Torrente, X. Federspiel, D. Rideau, F. Monsieur, C. Tavernier, J. Coignus, D. Roy, G. Ghibaudo
A complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented. After having underlined the need for a power law with a low exponent for the aging kinetics and considered a high activation energy reflecting the single electron impact mode, a fine calibration is achieved. Finally, analysis on trap distribution and aging rates at different channel locations are provided.
{"title":"Hot Carrier Stress modeling: From degradation kinetics to trap distribution evolution","authors":"G. Torrente, X. Federspiel, D. Rideau, F. Monsieur, C. Tavernier, J. Coignus, D. Roy, G. Ghibaudo","doi":"10.1109/IIRW.2015.7437086","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437086","url":null,"abstract":"A complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented. After having underlined the need for a power law with a low exponent for the aging kinetics and considered a high activation energy reflecting the single electron impact mode, a fine calibration is achieved. Finally, analysis on trap distribution and aging rates at different channel locations are provided.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125037926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437091
J. Holt, N. Cady, J. Yang-Scharlotta
Resistive memory (RRAM) is an emerging memory technology, expected to have inherent resistance to radiation damage. We present an initial study characterizing the effects of several types of radiation on a set of tantalum oxide-based RRAM devices. Gamma radiation (64.7 Mrad(Si)) was found to have no significant impact on switching properties. Likewise, ionic radiation (H, N, Ar+) up to 1015 ions/cm2 did not have any significant effect. This resistance to radiation, combined with high endurance and data retention, make RRAM an excellent candidate for use in harsh environments.
电阻式存储器(RRAM)是一种新兴的存储器技术，具有固有的抗辐射损伤能力。我们提出了一项初步研究，描述了几种类型的辐射对一组基于氧化钽的RRAM器件的影响。伽玛辐射(64.7 Mrad(Si))对开关特性没有显著影响。同样，离子辐射(H, N, Ar+)达到1015个离子/cm2时，也没有明显的影响。这种抗辐射能力，加上高耐用性和数据保留能力，使RRAM成为恶劣环境下使用的绝佳选择。
{"title":"Radiation testing of tantalum oxide-based resistive memory","authors":"J. Holt, N. Cady, J. Yang-Scharlotta","doi":"10.1109/IIRW.2015.7437091","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437091","url":null,"abstract":"Resistive memory (RRAM) is an emerging memory technology, expected to have inherent resistance to radiation damage. We present an initial study characterizing the effects of several types of radiation on a set of tantalum oxide-based RRAM devices. Gamma radiation (64.7 Mrad(Si)) was found to have no significant impact on switching properties. Likewise, ionic radiation (H, N, Ar+) up to 1015 ions/cm2 did not have any significant effect. This resistance to radiation, combined with high endurance and data retention, make RRAM an excellent candidate for use in harsh environments.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"694 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437084
Theodor Hillebrand, Nico Hellwege, N. Heidmann, S. Paul, D. Peters-Drolshagen
Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTI and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the gm/Id work flow or for yield estimation on circuit level.
{"title":"Charge-based stochastic aging analysis of CMOS circuits","authors":"Theodor Hillebrand, Nico Hellwege, N. Heidmann, S. Paul, D. Peters-Drolshagen","doi":"10.1109/IIRW.2015.7437084","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437084","url":null,"abstract":"Scaled down CMOS transistors are prone to degradation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTI and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the gm/Id work flow or for yield estimation on circuit level.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125711499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437083
M. Boubaaya, H. Tahi, Cherifa Tahanout, B. Djezzar, Abdelmadjid Benabdelmomene, A. Chenouf, D. Doumaz, Abdelhak Feraht Hemida
Instead, the classical consideration that the geometric component in charge pumping method (CP) is parasitic component, in this work we demonstrate that this component can be used to estimate the negative bias temperature (NBTI) induced mobility degradation using the charge pumping based method such as on- the-fly interface trap (OTFIT).
{"title":"Using the charge pumping geometric component to extract NBTI induced mobility degradation","authors":"M. Boubaaya, H. Tahi, Cherifa Tahanout, B. Djezzar, Abdelmadjid Benabdelmomene, A. Chenouf, D. Doumaz, Abdelhak Feraht Hemida","doi":"10.1109/IIRW.2015.7437083","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437083","url":null,"abstract":"Instead, the classical consideration that the geometric component in charge pumping method (CP) is parasitic component, in this work we demonstrate that this component can be used to estimate the negative bias temperature (NBTI) induced mobility degradation using the charge pumping based method such as on- the-fly interface trap (OTFIT).","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"104 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113963826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437062
C. Young, R. Campbell, S. Daasa, S. Benton, R. R. Rodriguez Davila, I. Mejia, M. Quevedo-López
We investigated the effects of hafnium oxide (HfO2) gate dielectric thickness and forming gas annealing on threshold voltage instability in zinc oxide thin film transistors using a variety of gate voltage - drain current testing methodologies. We found that dielectric thickness reduction and annealing significantly decreased the threshold voltage instability and the Vt reduction remained over an extended period of testing. Then, a similar investigation was conducted on zinc oxide thin-film transistors (ZnO TFT) with a thin layer of aluminum oxide (Al2O3) as the dielectric where a significant reduction in ΔVt was also observed.
{"title":"Effect of dielectric thickness and annealing on threshold voltage instability of low temperature deposited high-k oxides on ZnO TFTs","authors":"C. Young, R. Campbell, S. Daasa, S. Benton, R. R. Rodriguez Davila, I. Mejia, M. Quevedo-López","doi":"10.1109/IIRW.2015.7437062","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437062","url":null,"abstract":"We investigated the effects of hafnium oxide (HfO2) gate dielectric thickness and forming gas annealing on threshold voltage instability in zinc oxide thin film transistors using a variety of gate voltage - drain current testing methodologies. We found that dielectric thickness reduction and annealing significantly decreased the threshold voltage instability and the Vt reduction remained over an extended period of testing. Then, a similar investigation was conducted on zinc oxide thin-film transistors (ZnO TFT) with a thin layer of aluminum oxide (Al2O3) as the dielectric where a significant reduction in ΔVt was also observed.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117198154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437075
Z. Chbili, J. Chbili, J. Campbell, J. Ryan, M. Lahbabi, D. Ioannou, K. Cheung
This paper presents a novel experimental setup to perform wafer level TDDB testing. The massively parallel reliability system is capable of testing a total of 3000 probes simultaneously. The system can perform tests at temperatures up to 400 °C for high temperature applications (SiC). We also present TDDB results of SiO2 on SiC showing higher TDDB lifetime and field acceleration compared to SiO2 on Si.
{"title":"Massively parallel TDDB testing: SiC power devices","authors":"Z. Chbili, J. Chbili, J. Campbell, J. Ryan, M. Lahbabi, D. Ioannou, K. Cheung","doi":"10.1109/IIRW.2015.7437075","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437075","url":null,"abstract":"This paper presents a novel experimental setup to perform wafer level TDDB testing. The massively parallel reliability system is capable of testing a total of 3000 probes simultaneously. The system can perform tests at temperatures up to 400 °C for high temperature applications (SiC). We also present TDDB results of SiO2 on SiC showing higher TDDB lifetime and field acceleration compared to SiO2 on Si.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122974472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437068
Jen-Hao Lee, Eliot S. H. Chen, Yung-Huei Lee, C. Lin, Chun-Yu Wu, M. Hsieh, Kevin Huang, Jhong-Sheng Wang, Y. Tsai, R. Lu, J. Shih
Despite chip-package interaction (CPI) has been extensively used in nano-electronics industry, impact of CPI stress on transistor performance and reliability remains unclear. In this work, performance change of transistor featuring HK/MG planar and FinFET by 4-point bending experiments were conducted to study stress evolution. Finite-element modeling (FEM) simulation revealed that P-FinFET mobility change is less sensitive to applied stress than planar. Device reliability as BTI/HCI and ring oscillator frequency drift of both planar and FinFET are all immune to strain. Moreover, FinFET mobility degradation caused by NBTI is independent of strain type, due to its fully-depleted regime. Management of carrier mobility shifts and transistor aging by optimized chip package technology are also presented in this study.
{"title":"Reliability aging and modeling of chip-package interaction on logic technologies featuring high-k metal gate planar and FinFET transistors","authors":"Jen-Hao Lee, Eliot S. H. Chen, Yung-Huei Lee, C. Lin, Chun-Yu Wu, M. Hsieh, Kevin Huang, Jhong-Sheng Wang, Y. Tsai, R. Lu, J. Shih","doi":"10.1109/IIRW.2015.7437068","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437068","url":null,"abstract":"Despite chip-package interaction (CPI) has been extensively used in nano-electronics industry, impact of CPI stress on transistor performance and reliability remains unclear. In this work, performance change of transistor featuring HK/MG planar and FinFET by 4-point bending experiments were conducted to study stress evolution. Finite-element modeling (FEM) simulation revealed that P-FinFET mobility change is less sensitive to applied stress than planar. Device reliability as BTI/HCI and ring oscillator frequency drift of both planar and FinFET are all immune to strain. Moreover, FinFET mobility degradation caused by NBTI is independent of strain type, due to its fully-depleted regime. Management of carrier mobility shifts and transistor aging by optimized chip package technology are also presented in this study.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"11 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113942516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437080
S. Jayanarayanan
The resistance degradation of lightly doped Polysilicon Resistors (PR's) has been studied in detail, and the degradation rate statistically modelled. After accounting for Joule Heating [1], the resistance degradation is still observed to depend on current, indicating that current affects the degradation independent of Joule Heating.
{"title":"Polysilicon resistor degradation - modeling and mechanism","authors":"S. Jayanarayanan","doi":"10.1109/IIRW.2015.7437080","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437080","url":null,"abstract":"The resistance degradation of lightly doped Polysilicon Resistors (PR's) has been studied in detail, and the degradation rate statistically modelled. After accounting for Joule Heating [1], the resistance degradation is still observed to depend on current, indicating that current affects the degradation independent of Joule Heating.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117286048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437082
J. Coignus, A. Vernhet, G. Reimbold, G. Torrente, S. Renard, D. Roy
A novel Flash endurance characterization approach is presented, allowing delay-free READ operations and thus a realistic electrostatic description at each cycle before any device relaxation. Systematic measurement of time-dependent drain current during Hot Carrier programming is shown to provide an extended description of Flash programming dynamics with a 5ns time resolution, including tunnel oxide transport.
{"title":"Relaxation-free characterization of Flash programming dynamics along P-E cycling","authors":"J. Coignus, A. Vernhet, G. Reimbold, G. Torrente, S. Renard, D. Roy","doi":"10.1109/IIRW.2015.7437082","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437082","url":null,"abstract":"A novel Flash endurance characterization approach is presented, allowing delay-free READ operations and thus a realistic electrostatic description at each cycle before any device relaxation. Systematic measurement of time-dependent drain current during Hot Carrier programming is shown to provide an extended description of Flash programming dynamics with a 5ns time resolution, including tunnel oxide transport.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132925622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/IIRW.2015.7437059
C. Nguyen, C. Cagli, E. Vianello, A. Persico, G. Molas, G. Reimbold, Q. Rafhay, G. Ghibaudo
In this paper we present a high speed dynamical characterization of a HfO2-based Resistive Random Access Memory (RRAM) device. Thanks to a dedicated integrated device, in one Transistor one Resistor (1T1R) configuration, featuring an electrical pad between the selector and the memory cell, we provide very accurate programming measurements at the nanosecond range. The low parasitic capacitance (4pF) allows to detect and recording the transient voltage across the memory cell with a 400 ps resolution. The set voltage as a function of programming speed can thus be measured over a broad time range (10 ns-1 ms). The impact of the programming speed on the cell endurance is assessed. The effect of temperature on programming speed is also shown. It is demonstrated that the tested sample achieves SET with 1.3 V/15 ns pulse, and 1Mcycle is guaranteed with these programming conditions.
{"title":"Advanced 1T1R test vehicle for RRAM nanosecond-range switching-time resolution and reliability assessment","authors":"C. Nguyen, C. Cagli, E. Vianello, A. Persico, G. Molas, G. Reimbold, Q. Rafhay, G. Ghibaudo","doi":"10.1109/IIRW.2015.7437059","DOIUrl":"https://doi.org/10.1109/IIRW.2015.7437059","url":null,"abstract":"In this paper we present a high speed dynamical characterization of a HfO2-based Resistive Random Access Memory (RRAM) device. Thanks to a dedicated integrated device, in one Transistor one Resistor (1T1R) configuration, featuring an electrical pad between the selector and the memory cell, we provide very accurate programming measurements at the nanosecond range. The low parasitic capacitance (4pF) allows to detect and recording the transient voltage across the memory cell with a 400 ps resolution. The set voltage as a function of programming speed can thus be measured over a broad time range (10 ns-1 ms). The impact of the programming speed on the cell endurance is assessed. The effect of temperature on programming speed is also shown. It is demonstrated that the tested sample achieves SET with 1.3 V/15 ns pulse, and 1Mcycle is guaranteed with these programming conditions.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128468893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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