V. Putcha, Marko Simicic, P. Weckx, B. Parvais, J. Franco, B. Kaczer, D. Linten, D. Verkest, A. Thean, G. Groeseneken
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引用次数: 8
Abstract
Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.
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