FAULT MODELING AND TESTING OF GaAs STATIC RANDOM ACCESS MEMORIES

Abstract

Gallium Arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper analyzes the causes of these parametric faults by first mapping the observed errors in the fabrication process to circuit behavior; these modified circuits are then shown to cause new types of pattern-sensitive faults and data retention problems. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAM’s can be adequately tesled.