3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

T. Kawamoto, T. Norimatsu, K. Kogo, F. Yuki, N. Nakajima, M. Tsuge, T. Usugi, Tomofumi Hokari, H. Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, J. Kumazawa, Hiroaki Kurahashi, T. Muto, T. Yamashita, M. Hasegawa, K. Higeta
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引用次数: 23

Abstract

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.
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3.2 多标准 185fsrms 0.3-28Gb/s 40dB 背板信号调节器,采用 28nm CMOS 自适应模式匹配 36 抽头 DFE 和数据速率调整 PLL
随着处理速度和网络速度的加快,以支持数据丰富的服务,背板互连的带宽需要在保持通道长度和多速率链接的情况下提高。然而,在高数据速率下,信道损耗和阻抗不连续性会增加,因此很难对信道进行补偿。在这项工作中,我们的目标是在 40dB 背板架构中实现从 0.3Gb/s 的 100G-KR4 自动协商到 28.05Gb/s 的 32GFC 串行链路。要实现这一挑战,有两项关键技术。首先,我们引入了 36 抽头决策反馈均衡器 (DFE),以消除因连接器引起的反射,因为这些反射会关闭 "眼睛"。要操作 36 抽头 DFE,我们需要固定 CDR 锁定点并精确计算 36 抽头系数。因此,我们开发了带有 4b 图案滤波器的图案捕获 CDR 来固定锁定点,并开发了 3b 图案匹配自适应均衡器 (AEQ) 来优化 36 抽头系数。这些技术使我们的芯片能够补偿 40dB 的信道损耗。其次,我们的目标是 100G-KR4/40G-KR4/10G-KR/25G-KR 和 32GFC/16GFC/8GFC/4GFC。为了在 0.3 至 28.05Gb/s 的宽数据速率范围内以低抖动运行,我们开发了一种带有两个 LC-VCO 和一个环形 VCO 的 PLL 架构,并通过控制一个 LDO 采用了数据速率调整技术。我们的测试芯片采用 28nm CMOS 制作。我们的信号调节器通过使用 36 抽头 DFE 消除反射,在带两个连接器的 40dB 芯片到芯片背板上实现了 100G-KR4 的误码率 <;1012 PRBS31,并可在 0.3 至 28.05Gb/s 的宽数据速率范围内运行。
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