On the configuration of degradable VLSI/WSI arrays

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595639

C. Low, H. Leong

引用次数: 5

Abstract

The authors consider the problem of reconfiguring VLSI/WSI arrays via the degradation approach. In this approach, all elements are treated uniformly and no elements are dedicated as spares. The goal is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routing constraints. However, it is shown that a special case of the reconfiguration problem with row bypass and column rerouting capabilities, is solvable in polynomial time using network flows. Using this result, a new fast and efficient reconfiguration algorithm is proposed. Empirical study shows that the new algorithm indeed produces good results in terms of the percentages of harvest and degradation of VLSI/WSI arrays.

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可降解VLSI/WSI阵列的结构研究

作者考虑了利用退化方法重构VLSI/WSI阵列的问题。在这种方法中，所有元素都被统一处理，没有任何元素被专用为备用元素。目标是从有缺陷的主机阵列派生出无故障的子阵列T，使得T的维度大于某个指定的最小值。这个问题在各种交换和路由约束下是np完全的。然而，证明了具有行旁路和列重路由能力的重构问题的一个特殊情况，可以在多项式时间内使用网络流来解决。在此基础上，提出了一种新的快速高效的重构算法。实证研究表明，新算法在VLSI/WSI阵列的收获率和退化率方面确实取得了很好的效果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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