Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration

Abstract

We aim to fill the processing gap in 300 mm wafer-scale non-Bosch TSV etch process by developing production-worthy TSV etch solutions for logic-centric 3D integration. This is based on a magnetically-enhanced capacitively-coupled plasma (CCP) etching system. Key factors in this system that contribute to the control of via features such as global sidewall tapering, local sidewall roughness, Si etch rates, mask undercutting and local bowing effects were evaluated. The etching characteristics of anisotropic vias in silicon with nominal feature sizes of, but not limited to 5 µm × 25 µm (AR ∼ 5) and 1 µm × 20 µm (AR ∼ 20) with minimum pitches of 5 µm and 1 µm, respectively were quantified. 3 µm × 14 µm and 5 µm × 19 µm Cu-filled TSV are demonstrated by having continuous 2kÅ TEOS oxide liner/100 nm Ta(TaN) barrier/2kÅ Cu seed stack enabled by TSV etch.