Implantation-induced-defect generation during device fabrication on a SIMOX substrate

Abstract

One of the most important parameters in an SOI-DRAM process is to maintain an excellent gate oxide integrity. Recently, many papers related to microdefects in a SIMOX wafer itself, which cause gate oxide failure, have been reported. However, little study on process induced defects in real device fabrication, especially high density DRAMs, has been done. We find a crucial issue in SOI-DRAM on a SIMOX substrate is a high dose implantation-induced-defect generation (IIDG) during source/drain (S/D) implantation. We propose that a reduced S/D implantation dose is a key factor to achieve a high density DRAM and a possible mechanism for the IIDG in a SIMOX wafer is also discussed.