Fault tolerance in a wafer scale environment

Abstract

Methods of improving the probability that a message can be passed from one side of a wafer to another are presented. This is achieved by increasing the number of usable processors in the system or, in other words, lowering the percolation threshold. The impact of several underlying topologies is discussed in terms of a percolation theory framework. Also presented are new routing techniques for message passing in wafer scale integration (WSI) processor arrays. The algorithms forego the shortest path route so as to avoid faulty and congested areas of the network. They are based on a biased random walker approach where the direction each packet travels is determined locally at each processor by a nondeterministic algorithm and a set of bias values. A practical application motivated by improved connectivity in multichip modules is introduced. This method allows for a reconfigurable wafer backplane that provides advantages in bypassing faulty lines in the wafer.<>