Efficient Bidirectional protection structure for Plasma induced damage (PID) and Electrostatic discharge (ESD) for 3D IC Integration

Abstract

During metal/dielectric plasma processing for the back end of the line (BEOL), degradation of the transistor gate oxide may occur due to the plasma discharge current. This degradation can create a functional failure or lead to future reliability issues. Diodes of a specific size are incorporated into the chip to protect from plasma induced damage (PID) during the BEOL processing. In 3D integrated circuits (IC) additional processes such as through silicon via (TSV) etching and backside redistribution layer (RDL) are accounted for in deciding the diode size. Additional diode protection structure is also used for electrostatic discharge (ESD) damage during fab/assembly. In this study, a bidirectional diode is proposed to protect the transistor gate oxide from both PID and ESD during the 3D IC integration process. The combined protection diode addresses PID due to front and back side processes and ESD during chip to chip/wafer to wafer bonding process.