Complete tests in algorithm-based fault-tolerant matrix operation on processor arrays

Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems Pub Date : 1993-10-27 DOI:10.1109/DFTVS.1993.595819

D. Wei, J. H. Kim, T. Rao

引用次数: 5

Abstract

Recently, F. T. Assaad and S. Dutt (1992) proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the thresholded test in their approach is still not avoidable in the floating-point additions involved in matrix multiplication and the number of error detections decrease with the increase in the dynamic range of data, which is not totally satisfactory. The authors present an effective method, called concurrent floating-point checksum (CFPC) test, which provides very convincing error detection/correction capabilities for the part of floating-point addition with a minimum time latency and hardware overhead.

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处理器阵列上基于算法的容错矩阵运算的完整测试

最近，F. T. Assaad和S. Dutt(1992)提出了ABFT环境下浮点矩阵-矩阵乘法的混合校验和测试方法，这种方法可以大大提高误差覆盖率。然而，在矩阵乘法中涉及的浮点加法中，他们的方法仍然无法避免阈值测试，并且错误检测的次数随着数据动态范围的增加而减少，这并不完全令人满意。作者提出了一种有效的方法，称为并发浮点校验和(CFPC)测试，它以最小的时间延迟和硬件开销为浮点加法部分提供了非常令人信服的错误检测/纠正功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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