High-Performance and Energy-Efficient 256-Bit CMOS Priority Encoder

Abstract

A high-performance and energy-efficient 256-bit CMOS priority encoder is presented and realized on transistor level using 32 nm predictive technology. The new circuit is designed with a full custom approach and incorporates 2 novel logic styles: the Multiple-Output Monotonic CMOS (M2CMOS) and the Dynamic Inversion technique (DI). The achieved performance is in the order of O(log2(N)), with respect to the input size. A simulation-based comparative analysis concludes that, compared to the conventional design, the proposed circuit achieves up to 57% improvement in delay, 8% improvement in energy consumption and 39% improvement in EDP, while maintaining 20% smaller transistor count.